增加加密特性（未测试）

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -9,6 +9,8 @@ class CDRInIO extends Bundle{
   val axis = Decoupled(new AXIS_Bundle(8))
   val serDat = Input(Bool())
   val overCLK = Input(Bool())
+
+  val initEncryptor = Flipped(Valid(UInt(128.W)))
 }
 
 
@@ -17,6 +19,9 @@ abstract class CDRInBase extends Module{
 
   val io: CDRInIO = IO(new CDRInIO)
 
+  val encryptor = Module(new Encryptor)
+  encryptor.io.init := io.initEncryptor
+  encryptor.io.op.ready := io.axis.fire
 
 }
 
@@ -116,9 +121,9 @@ trait CDRInAxis{ this: CDRInBase =>
 
   val payloadLen = RegInit(0.U(12.W))
   when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
-    payloadLen := Cat( shiftData, 0.U(4.W) )
+    payloadLen := Cat( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), 0.U(4.W) )
   } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
-    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
+    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) )
   }
   
   stateNext := 
@@ -159,7 +164,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
   val axis_valid = RegInit(false.B)
-  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
+  val axis_tdata = RegEnable( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
   val axis_tuser = false.B
   val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )
 

src/main/scala/backBoard/ebus/CDROut.scala

@@ -13,13 +13,20 @@ class AXIS_Bundle(dw: Int) extends Bundle{
 class CDROutIO extends Bundle{
   val axis = Flipped(Decoupled(new AXIS_Bundle(8))) 
   val serDat = Output(Bool())
-}
 
+  val initEncryptor = Flipped(Valid(UInt(128.W)))
+
+}
 
 
 class CDROut extends Module{
   val io: CDROutIO = IO(new CDROutIO)
 
+  val encryptor = Module(new Encryptor)
+  encryptor.io.init := io.initEncryptor
+  encryptor.io.op.ready := io.axis.fire
+
+
   def STATE_IDLE  = 0.U
   def STATE_PREAMBLE = 1.U
   def STATE_PAYLOAD = 2.U
@@ -62,10 +69,10 @@ class CDROut extends Module{
       when( stateCurr === STATE_PREAMBLE ){
         shiftData := MuxCase( ETH_PRE, Array(
           ( byteCnt === 6.U ) -> ETH_SFD,
-          ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
+          ( byteCnt === 7.U ) -> Dualb4b5Encoder( io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) ),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
+        shiftData := Dualb4b5Encoder(io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) )
       }
     }
   }

src/main/scala/backBoard/shin/Interface.scala

@@ -13,9 +13,8 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
-  // val isSoftReset  = Bool()
   val encryptKey   = UInt(128.W)
-  // val isEncrypt    = Bool()
+  val isEncrypt    = Bool()
 
   // val upRecErrorCnt   = UInt(32.W)
   // val downRecErrorCnt = UInt(32.W)
@@ -169,6 +168,8 @@ class InterfaceIO extends Bundle{
 
   val sync = Output(Vec(4, Bool()))
 
+  val initEncryptor = Valid(UInt(128.W))
+
   val isSoftReset = Output(Bool())
 }
 
@@ -240,11 +241,14 @@ abstract class InterfaceBase extends Module{
 
 
 
+
+
       ((0 until 16).map{ i =>
         (addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
       Seq(
+        (addr === "h60".U ) -> cReg.isEncrypt,
         (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
         (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
         (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
@@ -449,7 +453,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
       }.reverse
     )
 
-
+  cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
@@ -733,8 +737,8 @@ with InterfaceSystem
   sReg.isDevOnRightModify := io.isDevOnRightModify
   sReg.indexOfRightDev    := io.indexOfRightDev
 
-
+  io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
-
+  io.initEncryptor.bits  := cReg.encryptKey
 
 
 }

src/main/scala/backBoard/shin/ShinTop.scala

@@ -67,18 +67,22 @@ abstract class ShinTopBase extends Module{
   val upCDROut   = Module(new CDROut)
 
   val interface = Module(new Interface)
-
   io.isSoftReset := interface.io.isSoftReset
 
   downCDRIn.io.serDat  := io.dDatIn
   downCDRIn.io.overCLK := io.clk8x
+  downCDRIn.io.initEncryptor := interface.io.initEncryptor
 
   upCDRIn.io.serDat  := io.uDatIn
   upCDRIn.io.overCLK := io.clk8x
+  upCDRIn.io.initEncryptor := interface.io.initEncryptor
 
   io.dDatOut := downCDROut.io.serDat
   io.uDatOut := upCDROut.io.serDat
 
+  downCDROut.io.initEncryptor := interface.io.initEncryptor
+  upCDROut.io.initEncryptor   := interface.io.initEncryptor
+
   //override
   when( slaveParser.io.isLoop & interface.io.cReg.modeSel === false.B){
     upCDRIn.io.serDat := downCDROut.io.serDat