增加加密特性（未测试）

src/main/scala/backBoard/shin/Interface.scala

@@ -13,9 +13,8 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
-  // val isSoftReset  = Bool()
   val encryptKey   = UInt(128.W)
-  // val isEncrypt    = Bool()
+  val isEncrypt    = Bool()
 
   // val upRecErrorCnt   = UInt(32.W)
   // val downRecErrorCnt = UInt(32.W)
@@ -169,6 +168,8 @@ class InterfaceIO extends Bundle{
 
   val sync = Output(Vec(4, Bool()))
 
+  val initEncryptor = Valid(UInt(128.W))
+
   val isSoftReset = Output(Bool())
 }
 
@@ -240,11 +241,14 @@ abstract class InterfaceBase extends Module{
 
 
 
+
+
       ((0 until 16).map{ i =>
         (addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
       Seq(
+        (addr === "h60".U ) -> cReg.isEncrypt,
         (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
         (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
         (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
@@ -449,7 +453,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
       }.reverse
     )
 
-
+  cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
@@ -733,8 +737,8 @@ with InterfaceSystem
   sReg.isDevOnRightModify := io.isDevOnRightModify
   sReg.indexOfRightDev    := io.indexOfRightDev
 
-
-
+  io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
+  io.initEncryptor.bits  := cReg.encryptKey
 
 
 }