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增加加密特性（未测试）

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This commit is contained in:
Ruige Lee
2025-05-22 16:53:42 +08:00
parent d14254f79a
commit 944255978a
4 changed files with 32 additions and 12 deletions
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11
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -9,6 +9,8 @@ class CDRInIO extends Bundle{
val axis = Decoupled(new AXIS_Bundle(8))
val serDat = Input(Bool())
val overCLK = Input(Bool())
val initEncryptor = Flipped(Valid(UInt(128.W)))
}
@@ -17,6 +19,9 @@ abstract class CDRInBase extends Module{
val io: CDRInIO = IO(new CDRInIO)
val encryptor = Module(new Encryptor)
encryptor.io.init := io.initEncryptor
encryptor.io.op.ready := io.axis.fire
}
@@ -116,9 +121,9 @@ trait CDRInAxis{ this: CDRInBase =>
val payloadLen = RegInit(0.U(12.W))
when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( shiftData, 0.U(4.W) )
payloadLen := Cat( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), 0.U(4.W) )
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) )
}
stateNext :=
@@ -159,7 +164,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )