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Merge branch 'ShinTop' into eb_dev

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bacon
2025-05-22 15:34:11 +08:00
parent 5ca43eea77 d14254f79a
commit 941a63b8ce
1 changed files with 50 additions and 14 deletions
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64
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -77,6 +77,15 @@ abstract class SlaveParserBase extends Module{
val FRAME_STYLE_COMMON = 0.U val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U val FRAME_STYLE_PROBE = 1.U
val SUBMSG_OPERATOR_UNIREAD = 0.U
val SUBMSG_OPERATOR_UNIWRITE = 1.U
val SUBMSG_OPERATOR_UNIRDWR = 2.U
val SUBMSG_OPERATOR_INDEX = "hb".U
val SUBMSG_OPERATOR_SYNC = "hc".U
val SUBMSG_OPERATOR_BOARDREAD = "hd".U
val SUBMSG_OPERATOR_BOARDWRITE = "he".U
val SUBMSG_OPERATOR_BOARDRDWR = "hf".U
val STATE_IDLE = 0.U //空闲 val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
@@ -343,7 +352,7 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
when( downRecParser.io.subMsgReq.fire & when( downRecParser.io.subMsgReq.fire &
downRecParser.io.subMsgReq.bits.devIndex === 0.U & downRecParser.io.subMsgReq.bits.devIndex === 0.U &
downRecParser.io.subMsgReq.bits.style === 0.U & downRecParser.io.subMsgReq.bits.style === 0.U &
downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址 downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U) indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U)
when( isDownRecPing ){ when( isDownRecPing ){
@@ -364,18 +373,23 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
trait SlaveParserRW{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase =>
//下行接收 //下行接收
when( downRecParser.io.subMsgReq.fire ){ when( downRecParser.io.subMsgReq.fire ){
when( isDownRecPing ){ when( isDownRecPing ){
//override //override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 2.U) ) ) { //自身包//写操作或读写操作) when(
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) { //自身包//写操作或读写操作)
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
} }
} .otherwise{ //pong } .otherwise{ //pong
//override //override
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 2.U) )) { //自身包//写操作或读写操作 ) when(
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) { //自身包//写操作或读写操作 )
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
} }
} }
@@ -395,8 +409,10 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & (downSubMsgInfo(0).devIndex === localDevIndex) & ( (downSubMsgInfo(0).operator === 1.U) | (downSubMsgInfo(0).operator === 2.U) )) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) |
( isDownRecPing & (downSubMsgInfo(1).devIndex === localDevIndex) & ( (downSubMsgInfo(1).operator === 1.U) | (downSubMsgInfo(1).operator === 2.U) )) ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) |
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) )
when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){ when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
@@ -429,19 +445,27 @@ trait SlaveParserRW{ this: SlaveParserBase =>
// val SUBMSG_OPERATOR_BOARDREAD = "hd".U
// val SUBMSG_OPERATOR_BOARDWRITE = "he".U
// val SUBMSG_OPERATOR_BOARDRDWR = "hf".U
//上行接收 //上行接收
when( upRecParser.io.subMsgReq.fire ){ when( upRecParser.io.subMsgReq.fire ){
when( isUpRecPing ){ when( isUpRecPing ){
//override //override
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 0.U) || (upRecParser.io.subMsgReq.bits.operator === 2.U) ) ){ //自身包//读或读写 when(
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
){ //自身包//读或读写
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
} }
} .otherwise{ } .otherwise{
//override //override
when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 0.U) || (upRecParser.io.subMsgReq.bits.operator === 2.U) )){ //自身包//读或读写 ) when(
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
){ //自身包//读或读写 )
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
} }
} }
@@ -455,10 +479,11 @@ trait SlaveParserRW{ this: SlaveParserBase =>
//读出uSM //读出uSM
val isRead = val isRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 0.U | upSubMsgInfo(0).operator === 2.U)) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) |
( isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 0.U | upSubMsgInfo(1).operator === 2.U)) ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
) )
//| ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 0.U | upRecParser.io.subMsgReq.bits.operator === 2.U))
) )
val addrr = Reg(UInt(15.W)) val addrr = Reg(UInt(15.W))
@@ -486,10 +511,16 @@ trait SlaveParserRW{ this: SlaveParserBase =>
isRDSM7 -> io.sram_r(3).datar, isRDSM7 -> io.sram_r(3).datar,
)) ))
when( ~isUpRecPing ){ //req fire 后 已经反相 when( ~isUpRecPing ){ //req fire 后 已经反相
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
upRecFifo(0).io.enq.bits := upRecFifo(0).io.enq.bits :=
Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 0.U | upSubMsgInfo(0).operator === 2.U), Mux( upSubMsgInfo(0).devIndex === localDevIndex & (
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD |
upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR
),
upStreamData, upRecParser.io.data.bits) upStreamData, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
@@ -501,7 +532,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
upRecFifo(1).io.enq.bits := upRecFifo(1).io.enq.bits :=
Mux( upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 0.U | upSubMsgInfo(1).operator === 2.U), Mux( upSubMsgInfo(1).devIndex === localDevIndex & (
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD |
upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR
),
upStreamData, upRecParser.io.data.bits) upStreamData, upRecParser.io.data.bits)
upRecParser.io.data.ready := upRecFifo(1).io.enq.ready upRecParser.io.data.ready := upRecFifo(1).io.enq.ready