diff --git a/src/main/scala/backBoard/goWinBus.scala b/src/main/scala/backBoard/goWinBus.scala
new file mode 100644
index 0000000..7a695f3
--- /dev/null
+++ b/src/main/scala/backBoard/goWinBus.scala
@@ -0,0 +1,190 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+class CRC_ERR_Bundle extends Bundle{
+  val crc_err       = Bool()
+  val crc_err_count = UInt(8.W)
+  val cdr_err       = Bool()
+}
+
+class Lvds_Bus_MasterIO extends Bundle{
+  val rst_n     = Input(Bool())
+  val oser_pclk = Input(Bool())
+  val oser_fclk = Input(Bool())
+  val ides_pclk = Input(Bool())
+  val ides_fclk = Input(Bool())
+  
+  val lvds_down_dout = Output(Bool())
+  val lvds_up_din    = Input(Bool())
+    
+  val frame_info_update_en = Input(Bool())
+  val slave_type_num       = Input(UInt(8.W))
+  val slave_data_length    = Input(UInt(8.W))
+  val tx_start             = Input(Bool())
+  val tx_data_in           = Input(UInt(8.W))
+  val tx_data_ready        = Output(Bool())
+  val downstream_busy      = Output(Bool())
+  val rx_data_out          = Output(UInt(8.W))
+  val rx_data_valid        = Output(Bool())
+
+  val upstream_crc_valid     = Output(Bool())
+  val upstream_crc_err       = Output(Bool())
+  val upstream_crc_err_count = Output(UInt(8.W))
+  val upstream_cdr_err       = Output(Bool())
+
+}
+
+class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
+
+  val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
+
+  setInline("lvds_bus_master.v",
+              """
+  | module Lvds_Bus_Master(
+  | input rst_n,
+  | input oser_pclk,
+  | input oser_fclk,
+  | input ides_pclk,
+  | input ides_fclk,
+  | output lvds_down_dout,
+  | input lvds_up_din,
+  | input frame_info_update_en,
+  | input [7:0] slave_type_num,
+  | input [7:0]slave_data_length,
+  | input tx_start,
+  | input [7:0] tx_data_in,
+  | output tx_data_ready,
+  | output downstream_busy,
+  | output [7:0] rx_data_out,
+  | output rx_data_valid,
+  | output upstream_crc_valid,
+  | output upstream_crc_err,
+  | output [7:0] upstream_crc_err_count,
+  | output upstream_cdr_err
+  | );
+  | lvds_bus_master_top i_lvds_bus_master(
+  |   .rst_n(rst_n), //input
+  |   .oser_pclk(oser_pclk), //input 
+  |   .oser_fclk(oser_fclk), //input  
+  |   .ides_pclk(ides_pclk), //input
+  |   .ides_fclk(ides_fclk), //input
+  | 
+  |   .lvds_down_dout(lvds_down_dout), //output
+  |   .lvds_up_din(lvds_up_din), //input
+  |   
+  |   .frame_info_update_en(frame_info_update_en), //input 
+  |   .slave_type_num(slave_type_num), //input [7:0]     
+  |   .slave_data_length(slave_data_length), //input [7:0]
+  |   .tx_start(tx_start), //input   
+  |   .tx_data_in(tx_data_in), //input [7:0]  
+  |   .tx_data_ready(tx_data_ready), //output
+  |   .downstream_busy(downstream_busy), //output 
+  |   .rx_data_out(rx_data_out), //output [7:0]
+  |   .rx_data_valid(rx_data_valid), //output
+  |   .upstream_crc_valid(upstream_crc_valid), //output
+  |   .upstream_crc_err(upstream_crc_err), //output
+  |   .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
+  |   .upstream_cdr_err(upstream_cdr_err) //output 
+  | );
+  |endmodule
+    """.stripMargin)
+}
+
+class Lvds_Bus_SlaveIO extends Bundle{
+  val rst_n     = Input(Bool())
+  val oser_pclk = Input(Bool())
+  val oser_fclk = Input(Bool())
+  val ides_pclk = Input(Bool())
+  val ides_fclk = Input(Bool())
+  
+
+  val lvds_down_din  = Input(Bool())
+  val lvds_down_dout = Output(Bool())
+  val lvds_up_din    = Input(Bool())
+  val lvds_up_dout   = Output(Bool())
+    
+  val downstream_rx_data_valid = Output(Bool())
+  val downstream_rx_data_out   = Ouyput(UInt(8.W))
+  val downstream_rx_crc_valid  = Output(Bool())
+  val downstream_rx_crc_err = Output(Bool())
+  val downstream_rx_crc_err_counter = Output(UInt(8.W))
+  val downstream_rx_cdr_err = Output(Bool())
+  val downstream_sync = Output(Bool())
+
+  val upstream_tx_data_ready = Output(Bool())
+  val upstream_tx_data_in = Input(UInt(8.W))
+
+  val upstream_rx_crc_valid = Output(Bool())
+  val upstream_rx_crc_err = Output(Bool())
+  val upstream_rx_crc_err_counter = Output(UInt(8.W))
+  val upstream_rx_cdr_err = Output(Bool())
+}
+
+
+
+class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
+  val io: Lvds_Bus_SlaveIO = IO(new Lvds_Bus_SlaveIO)
+
+  setInline("lvds_bus_master.v",
+              """
+  module Lvds_Bus_Slave(
+  |  input rst_n,
+  |  input oser_pclk,
+  |  input oser_fclk,
+  |  input ides_pclk,
+  |  input ides_fclk,
+  |  
+  |  input lvds_down_din,
+  |  output lvds_down_dout,
+  |  input lvds_up_din,
+  |  output lvds_up_dout,
+  |  
+  |  output downstream_rx_data_valid,
+  |  output [7:0] downstream_rx_data_out,
+  |  output downstream_rx_crc_valid,
+  |  output downstream_rx_crc_err,
+  |  output [7:0] downstream_rx_crc_err_counter,
+  |  output downstream_rx_cdr_err,
+  |  output downstream_sync,
+  |  output upstream_tx_data_ready,
+  |  input [7:0] upstream_tx_data_in,
+  |  output upstream_rx_crc_valid,
+  |  output upstream_rx_crc_err,
+  |  output [7:0] upstream_rx_crc_err_counter,
+  |  output upstream_rx_cdr_err
+  |);
+  |
+  |  lvds_bus_slave_top i_lvds_bus_slave(
+  |  .rst_n(rst_n),
+  |  .oser_pclk(oser_pclk),
+  |  .oser_fclk(oser_fclk),
+  |  .ides_pclk(ides_pclk),
+  |  .ides_fclk(ides_fclk),
+  |  
+  |  .lvds_down_din(lvds_down_din),
+  |  .lvds_down_dout(lvds_down_dout),
+  |  .lvds_up_din(lvds_up_din),
+  |  .lvds_up_dout(lvds_up_dout),
+  |  
+  |  .downstream_rx_data_valid(downstream_rx_data_valid), 
+  |  .downstream_rx_data_out(downstream_rx_data_out),
+  |  .downstream_rx_crc_valid(downstream_rx_crc_valid),
+  |  .downstream_rx_crc_err(downstream_rx_crc_err),
+  |  .downstream_rx_crc_err_counter(downstream_rx_crc_err_counter),
+  |  .downstream_rx_cdr_err(downstream_rx_cdr_err),
+  |  .downstream_sync(downstream_sync),
+  |  .upstream_tx_data_ready(upstream_tx_data_ready),
+  |  .upstream_tx_data_in(upstream_tx_data_in),
+  |  .upstream_rx_crc_valid(upstream_rx_crc_valid),
+  |  .upstream_rx_crc_err(upstream_rx_crc_err),
+  |  .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter),
+  |  .upstream_rx_cdr_err(upstream_rx_cdr_err)
+  |  );
+  |endmodule
+    """.stripMargin)
+}
+
diff --git a/src/main/scala/backBoard/goWinMst.scala b/src/main/scala/backBoard/goWinMst.scala
deleted file mode 100644
index ce282fa..0000000
--- a/src/main/scala/backBoard/goWinMst.scala
+++ /dev/null
@@ -1,70 +0,0 @@
-package BACK
-
-import chisel3._
-import chisel3.util._
-
-
-
-class CRC_ERR_Bundle extends Bundle{
-  val crc_err       = Bool()
-  val crc_err_count = UInt(8.W)
-  val cdr_err       = Bool()
-}
-
-  class Lvds_Bus_MasterIO extends Bundle{
-    val rst_n     = Input(Bool())
-    val oser_pclk = Input(Bool())
-    val oser_fclk = Input(Bool())
-    val ides_pclk = Input(Bool())
-    val ides_fclk = Input(Bool())
-   
-    val lvds_down_dout = Output(Bool())
-    val lvds_up_din    = Input(Bool())
-     
-    val frame_info_update_en = Input(Bool())
-    val slave_type_num       = Input(UInt(8.W))
-    val slave_data_length    = Input(UInt(8.W))
-    val tx_start             = Input(Bool())
-    val tx_data_in           = Input(UInt(8.W))
-    val tx_data_ready        = Output(Bool())
-    val downstream_busy      = Output(Bool())
-    val rx_data_out          = Output(UInt(8.W))
-    val rx_data_valid        = Output(Bool())
-
-    val upstream_crc = Valid(new CRC_ERR_Bundle)
-
-  }
-
-class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
-
-  val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
-
-  setInline("lvds_bus_master.v",
-              """
-  | lvds_bus_master_top your_instance_name(
-  |   .rst_n(rst_n), //input
-  |   .oser_pclk(oser_pclk), //input 
-  |   .oser_fclk(oser_fclk), //input  
-  |   .ides_pclk(ides_pclk), //input
-  |   .ides_fclk(ides_fclk), //input
-  | 
-  |   .lvds_down_dout(lvds_down_dout), //output
-  |   .lvds_up_din(lvds_up_din), //input
-  |   
-  |   .frame_info_update_en(frame_info_update_en), //input 
-  |   .slave_type_num(slave_type_num), //input [7:0]     
-  |   .slave_data_length(slave_data_length), //input [7:0]
-  |   .tx_start(tx_start), //input   
-  |   .tx_data_in(tx_data_in), //input [7:0]  
-  |   .tx_data_ready(tx_data_ready), //output
-  |   .downstream_busy(downstream_busy), //output 
-  |   .rx_data_out(rx_data_out), //output [7:0]
-  |   .rx_data_valid(rx_data_valid), //output
-  |   .upstream_crc_valid(upstream_crc_valid), //output
-  |   .upstream_crc_err(upstream_crc_err), //output
-  |   .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
-  |   .upstream_cdr_err(upstream_cdr_err) //output 
-  | );
-    """.stripMargin)
-}
-