move out rx
This commit is contained in:
RuigeLee
@@ -38,8 +38,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val ShortFrame = Input(Bool()) // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
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val DribbleNibble = Input(Bool()) // Extra nibble received
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val ReceivedPacketTooBig = Input(Bool()) // Received packet is bigger than r_MaxFL
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val RxLength = Input(UInt(16.W)) // Length of the incoming frame
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val LoadRxStatus = Input(Bool()) // Rx status was loaded
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val ReceivedPacketGood = Input(Bool()) // Received packet's length and CRC are good
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val AddressMiss = Input(Bool()) // When a packet is received AddressMiss status is written to the Rx BD
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val r_RxFlow = Input(Bool())
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@@ -62,11 +60,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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// Rx
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val MRxClk = Input(Bool()) // Receive clock (from PHY)
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val RxData = Input(UInt(8.W)) // Received data byte (from PHY)
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val RxValid = Input(Bool())
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val RxStartFrm = Input(Bool())
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val RxEndFrm = Input(Bool())
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val RxAbort = Input(Bool()) // This signal is set when address doesn't match.
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val RxStatusWriteLatched_sync2 = Output(Bool())
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//Register
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@@ -98,6 +91,21 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxRetrySync = Input(Bool())
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val TxAbortSync = Input(Bool()) // Transmit packet abort
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val TxDoneSync = Input(Bool()) // Transmission ended
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val RxDataLatched2_rxclk = Input(UInt(32.W))
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val WriteRxDataToFifoSync = Input(Bool())
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val RxAbortSync = Input(Bool())
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val LatchedRxLength_rxclk = Input(UInt(16.W))
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val RxStatusInLatched_rxclk = Input(UInt(9.W))
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val ShiftEndedSync = Input(Bool())
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val SyncRxStartFrmSync = Input(Bool())
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val Busy_IRQ_sync = Input(Bool())
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val RxReady = Output(Bool())
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val RxStatusIn = Output(UInt(9.W))
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}
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@@ -148,7 +156,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxAbortPacket = RegInit(false.B)
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val TxAbortPacket_NotCleared = RegInit(false.B)
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val RxBDReady = RegInit(false.B)
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val RxReady = RegInit(false.B)
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val RxReady = RegInit(false.B); io.RxReady := RxReady
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val TxBDReady = RegInit(false.B)
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val RxBDRead = RegInit(false.B)
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@@ -234,12 +242,9 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val RxPointerRead = RegInit(false.B)
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// RX shift ending signals
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val ShiftEnded_rck_rxclk = Wire(Bool())
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// val ShiftEndedSync1 = RegNext( ShiftEnded_rck_rxclk, false.B)
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// val ShiftEndedSync2 = RegNext( ShiftEndedSync1, false.B)
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val ShiftEndedSync3 = RegInit(false.B)
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val ShiftEndedSync = ShiftRegisters( ShiftEnded_rck_rxclk, 2, false.B, true.B )
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@@ -280,20 +285,18 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val RxAbortLatched_rxclk = Wire(Bool())
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val RxAbortSync = ShiftRegisters( RxAbortLatched_rxclk, 4, false.B, true.B )
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val WriteRxDataToFifo_rxclk = Wire(Bool())
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val WriteRxDataToFifoSync = ShiftRegisters(WriteRxDataToFifo_rxclk, 3, false.B, true.B)
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val RxAbortPluse = io.RxAbortSync & RegNext(io.RxAbortSync, false.B)
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val LatchedRxStartFrm_rxclk = Wire(Bool())
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val SyncRxStartFrmSync = ShiftRegisters(LatchedRxStartFrm_rxclk, 3, false.B, true.B)
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val RxStatusWriteLatched = RegInit(false.B)
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val RxStatusWriteLatched_syncb = ShiftRegister(io.RxStatusWriteLatched_sync2, 2, false.B, true.B)
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io.RxStatusWriteLatched_sync2 := ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B)
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@@ -660,9 +663,9 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxStatusInLatched = Cat(io.TxUnderRun, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
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val LatchedRxLength_rxclk = Wire(UInt(16.W))
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val RxStatusInLatched_rxclk = Wire(UInt(9.W))
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RxBDDataIn := Cat(LatchedRxLength_rxclk, 0.U(1.W), RxStatus, 0.U(4.W), RxStatusInLatched_rxclk)
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RxBDDataIn := Cat(io.LatchedRxLength_rxclk, 0.U(1.W), RxStatus, 0.U(4.W), io.RxStatusInLatched_rxclk)
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TxBDDataIn := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), TxStatusInLatched)
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@@ -771,7 +774,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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ReadTxDataFromFifo_wb := io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
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val StartRxBDRead = RxStatusWrite | (RxAbortSync(2) & ~RxAbortSync(3)) | (io.r_RxEn & ~r_RxEn_q)
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val StartRxBDRead = RxStatusWrite | RegNext(RxAbortPluse, false.B) | (io.r_RxEn & ~r_RxEn_q)
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// Reading the Rx buffer descriptor
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when(StartRxBDRead & ~RxReady){
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@@ -800,7 +803,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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// RxReady generation
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when(ShiftEnded | RxAbortSync(1) & ~RxAbortSync(2) | ~io.r_RxEn & r_RxEn_q){
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when(ShiftEnded | RxAbortPluse | ~io.r_RxEn & r_RxEn_q){
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RxReady := false.B
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} .elsewhen(stateNxt === StateRX & stateCur === StateRX & RxPointerRead){
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RxReady := true.B
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@@ -840,12 +843,12 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val WriteRxDataToFifo_wb = WriteRxDataToFifoSync(1) & ~WriteRxDataToFifoSync(2)
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val RxFifoReset = SyncRxStartFrmSync(1) & ~SyncRxStartFrmSync(2)
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val WriteRxDataToFifo_wb = io.WriteRxDataToFifoSync & ~RegNext(io.WriteRxDataToFifoSync, false.B)
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val RxFifoReset = io.SyncRxStartFrmSync & ~RegNext(io.SyncRxStartFrmSync, false.B)
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val rx_fifo = Module(new MacFifo(dw = 32, dp = 16))
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val RxDataLatched2_rxclk = Wire(UInt(32.W))
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rx_fifo.io.data_in := RxDataLatched2_rxclk
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rx_fifo.io.data_in := io.RxDataLatched2_rxclk
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rx_fifo.io.write := WriteRxDataToFifo_wb & ~RxBufferFull
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rx_fifo.io.read := MasterWbRX & io.tlMst.A.fire
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rx_fifo.io.clear := RxFifoReset
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@@ -867,7 +870,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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when(ShiftEndedSync(0) & ~ShiftEndedSync(1)){
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when( io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B)){
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ShiftEndedSync3 := true.B
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} .elsewhen(ShiftEnded){
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ShiftEndedSync3 := false.B
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@@ -884,7 +887,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val RxStatusIn = Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
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io.RxStatusIn := Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
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// Rx overrun
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@@ -901,7 +904,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames are aborted when signal r_RecSmall is set to 0 in MODER register.
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// AddressMiss is identifying that a frame was received because of the promiscous mode and is not an error
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val RxError = (RxStatusInLatched_rxclk(6,3).orR) | (RxStatusInLatched_rxclk(1,0).orR)
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val RxError = (io.RxStatusInLatched_rxclk(6,3).orR) | (io.RxStatusInLatched_rxclk(1,0).orR)
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// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
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@@ -946,7 +949,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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io.Busy_IRQ := io.Busy_IRQ_sync & ~RegNext(io.Busy_IRQ_sync)
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@@ -1119,50 +1122,43 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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trait MacTileLinkRXClk{ this: MacTileLinkBase =>
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val macTileLinkRX = withClockAndReset( io.MRxClk.asClock, io.asyncReset ) ( Module(new MacTileLinkRX) )
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RxDataLatched2_rxclk := macTileLinkRX.io.RxDataLatched2
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WriteRxDataToFifo_rxclk := macTileLinkRX.io.WriteRxDataToFifo
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RxAbortLatched_rxclk := macTileLinkRX.io.RxAbortLatched
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LatchedRxLength_rxclk := macTileLinkRX.io.LatchedRxLength
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RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched
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ShiftEnded_rck_rxclk := macTileLinkRX.io.ShiftEnded_rck
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LatchedRxStartFrm_rxclk := macTileLinkRX.io.LatchedRxStartFrm
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// val macTileLinkRX = withClockAndReset( io.MRxClk.asClock, io.asyncReset ) ( Module(new MacTileLinkRX) )
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// RxDataLatched2_rxclk := macTileLinkRX.io.RxDataLatched2
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// WriteRxDataToFifo_rxclk := macTileLinkRX.io.WriteRxDataToFifo
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// RxAbortLatched_rxclk := macTileLinkRX.io.RxAbortLatched
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// LatchedRxLength_rxclk := macTileLinkRX.io.LatchedRxLength
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// RxStatusInLatched_rxclk := macTileLinkRX.io.RxStatusInLatched
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// ShiftEnded_rck_rxclk := macTileLinkRX.io.ShiftEnded_rck
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// LatchedRxStartFrm_rxclk := macTileLinkRX.io.LatchedRxStartFrm
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// Busy Interrupt
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val Busy_IRQ_sync = ShiftRegisters(macTileLinkRX.io.Busy_IRQ_rck, 3)
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io.Busy_IRQ := Busy_IRQ_sync(1) & ~Busy_IRQ_sync(2)
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// // Busy Interrupt
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// val Busy_IRQ_sync = ShiftRegisters(macTileLinkRX.io.Busy_IRQ_rck, 3)
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// io.Busy_IRQ := Busy_IRQ_sync(1) & ~Busy_IRQ_sync(2)
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withClockAndReset( io.MRxClk.asClock, io.asyncReset ) {
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macTileLinkRX.io.ShiftEndedSync := ShiftRegisters(ShiftEndedSync(1), 2, false.B, true.B)
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macTileLinkRX.io.RxAbortSyncb := ShiftRegister( RxAbortSync(1), 2, false.B, true.B )
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io.RxStatusWriteLatched_sync2 := ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B)
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macTileLinkRX.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B )
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macTileLinkRX.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync(1), 2, false.B, true.B )
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macTileLinkRX.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync(1), 2, false.B, true.B )
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macTileLinkRX.io.RxReady := ShiftRegister( RxReady, 2, false.B, true.B )
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}
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macTileLinkRX.io.RxData := io.RxData
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macTileLinkRX.io.RxAbort := io.RxAbort
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macTileLinkRX.io.RxValid := io.RxValid
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macTileLinkRX.io.RxStartFrm := io.RxStartFrm
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macTileLinkRX.io.RxEndFrm := io.RxEndFrm
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macTileLinkRX.io.RxLength := io.RxLength
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macTileLinkRX.io.LoadRxStatus := io.LoadRxStatus
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macTileLinkRX.io.RxStatusIn := RxStatusIn
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// withClockAndReset( io.MRxClk.asClock, io.asyncReset ) {
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// macTileLinkRX.io.ShiftEndedSync := ShiftRegisters(ShiftEndedSync(1), 2, false.B, true.B)
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// macTileLinkRX.io.RxAbortSyncb := ShiftRegister( RxAbortSync(1), 2, false.B, true.B )
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// io.RxStatusWriteLatched_sync2 := ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B)
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// macTileLinkRX.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B )
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// macTileLinkRX.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync(1), 2, false.B, true.B )
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// macTileLinkRX.io.SyncRxStartFrmSyncb := ShiftRegister( SyncRxStartFrmSync(1), 2, false.B, true.B )
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// macTileLinkRX.io.RxReady := ShiftRegister( RxReady, 2, false.B, true.B )
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// }
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// macTileLinkRX.io.RxData := io.RxData
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// macTileLinkRX.io.RxAbort := io.RxAbort
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// macTileLinkRX.io.RxValid := io.RxValid
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// macTileLinkRX.io.RxStartFrm := io.RxStartFrm
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// macTileLinkRX.io.RxEndFrm := io.RxEndFrm
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// macTileLinkRX.io.RxLength := io.RxLength
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// macTileLinkRX.io.LoadRxStatus := io.LoadRxStatus
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// macTileLinkRX.io.RxStatusIn := RxStatusIn
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}
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@@ -1460,7 +1456,7 @@ class MacTileLinkRXIO extends Bundle{
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val RxLength = Input(UInt(16.W))
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val LoadRxStatus = Input(Bool())
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val RxStatusIn = Input(UInt(9.W))
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val ShiftEndedSync = Input(Vec(2,Bool()) )
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val ShiftEndedSyncb = Input(Bool())
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val RxAbortSyncb = Input(Bool())
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val WriteRxDataToFifoSyncb = Input(Bool())
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val SyncRxStartFrmSyncb = Input(Bool())
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@@ -1580,7 +1576,7 @@ class MacTileLinkRX extends Module with RequireAsyncReset{
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// Generation of the end-of-frame signal
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when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
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ShiftEnded_rck := true.B
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} .elsewhen(io.RxAbort | io.ShiftEndedSync(0) & io.ShiftEndedSync(1)){
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} .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){
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ShiftEnded_rck := false.B
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}
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@@ -1647,7 +1643,7 @@ class MacTileLinkRX extends Module with RequireAsyncReset{
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// val RxStatusInLatched = RegEnable(RxStatusIn, 0.U(9.W), io.LoadRxStatus); RxStatusInLatched_rxclk := RxStatusInLatched
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// val ShiftEnded_rck = RegInit(false.B); ShiftEnded_rck_txclk := ShiftEnded_rck
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// val ShiftEndedSync = ShiftRegisters(ShiftEndedSync2, 2, false.B, true.B)
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// val ShiftEndedSyncb = ShiftRegisters(ShiftEndedSync2, 2, false.B, true.B)
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// val RxAbortSyncb = ShiftRegister( RxAbortSync(1), 2, false.B, true.B )
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@@ -1729,7 +1725,7 @@ class MacTileLinkRX extends Module with RequireAsyncReset{
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// // Generation of the end-of-frame signal
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// when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
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// ShiftEnded_rck := true.B
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// } .elsewhen(io.RxAbort | ShiftEndedSync(0) & ShiftEndedSync(1)){
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// } .elsewhen(io.RxAbort | ShiftEndedSyncb(0) & ShiftEndedSyncb(1)){
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// ShiftEnded_rck := false.B
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// }
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Block a user