From 9291c6eba59adf3275e017dcebcfc5705167d71c Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 11 Feb 2025 17:34:24 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=8F=8D=E6=B1=87=E7=BC=96?= =?UTF-8?q?=E9=87=8C=E7=9A=84=E6=BA=90=E4=BB=A3=E7=A0=81=EF=BC=8C=E4=BE=BF?= =?UTF-8?q?=E4=BA=8E=E4=B8=8EC=E8=AF=AD=E8=A8=80=E5=AF=B9=E5=BA=94?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 18a52ac..f8f48aa 100644 --- a/Makefile +++ b/Makefile @@ -145,7 +145,7 @@ sw: $(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin - $(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump + $(TARGET)-objdump --disassemble-all -S --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump $(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog @@ -215,7 +215,7 @@ sw: $(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin - $(TARGET)-objdump -S -s --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump + $(TARGET)-objdump -S --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump $(TARGET)-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog