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修改测试时钟偏差的仿真测试思路

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This commit is contained in:
bacon
2025-09-22 15:39:22 +08:00
parent 5620be6b04
commit 8ed508f655
4 changed files with 109 additions and 251 deletions
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50
tb/shinTest/Makefile_vcs
View File

@@ -4,6 +4,7 @@ OUTPUT = shin_test
CPU_COUNT := $(shell nproc)
SPI_TYPE ?= -spi 0
TRANS_CODE ?=
DEVCLK ?= --dev1 0 90 --dev2 0 -90
VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
-full64 \
@@ -25,59 +26,12 @@ testShin_vcs:
python3 ./shinTest/check_testcase.py
testShinClk_vcs:
python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90
python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data1.txt
mv generated/wave.vcd generated/wave1.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 70 -180 -8b10b
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data2.txt
mv generated/wave.vcd generated/wave2.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 185 --dev3 25 -185
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data3.txt
mv generated/wave.vcd generated/wave3.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 60 186 --dev3 15 -186
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data4.txt
mv generated/wave.vcd generated/wave4.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 80 187 --dev2 30 -187
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data5.txt
mv generated/wave.vcd generated/wave5.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 70 188 --dev3 223 -188 -8b10b
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data6.txt
mv generated/wave.vcd generated/wave6.vcd
testShinMany_vcs:

4
tb/shinTest/ShinTopSpiTb.v
View File

@@ -540,7 +540,6 @@ end
//DEV_NUM
//ALL_DEV_NUM
wire isQspi = (idx >= 0 && idx <= (`ALL_DEV_NUM - 1)) || idx >= (`ALL_DEV_NUM * 2);
wire isAQspi = (idx >= (`ALL_DEV_NUM * 3));
wire [11:0] nextByteCnt = byteCnt + 1;
//输出
@@ -608,7 +607,7 @@ end
//mst slv0~slv3的 内部qspi调用即设置
//sidx为0~4；外部spi为5~9，外部qspi为10~15
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [16:0] sidx );
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, input [16:0] sidx );
begin
txBuf[0] <= saddress[15:8];
txBuf[1] <= saddress[7:0];
@@ -660,7 +659,6 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
)
) begin
for (integer _k = 0; _k < 4; _k++) begin
if (scmd == 0) begin
$fwrite(spidata_file, "%02h ", txBuf[_k + _pos]);

296
tb/shinTest/ShinTopSpiTb_clk.v
View File

@@ -1,8 +1,5 @@
`timescale 1 ns / 1 ps
`define ENABLE_REG_RW1_TEST "generated/log/reg_rw1_tc.log"
module ShinTopSpiTb(
);
@@ -12,12 +9,13 @@ module ShinTopSpiTb(
reg [15:0] multiCLK;
`include "dev_predef.vh"
`ifdef DEFINE_SLAVE_DEVICE
`define DEV_NUM 4 //slave num
`define ALL_DEV_NUM (`DEV_NUM + 1) // slave + master
`define SPI_CSN_NUM (`ALL_DEV_NUM * 3)
`define SPI_CSN_NUM (`ALL_DEV_NUM * 4)
`define HW_SERIAL 0 //48'h31303050584c //(48'h4c5850303031)
`define IQSPI_PINS(N) (`N*4+3):(`N*4)
@@ -61,7 +59,7 @@ module ShinTopSpiTb(
wire qspi_sck;
wire [3:0] qspi_mosi;
//wire [40-1:0] qspi_miso;
wire [(`ALL_DEV_NUM * 4 * 2 - 1):0] qspi_miso;
wire [(`ALL_DEV_NUM * 4 * 3 - 1):0] qspi_miso;
integer spidata_file;
integer c_line;
@@ -136,6 +134,12 @@ ShinTop s_ShinTop_Mst(
.io_oqspi_isDirIn(),
.io_oqspi_csn(`EQSPI_CSN(0)),
.io_aqspi_sck(qspi_sck),
.io_aqspi_mosi(qspi_mosi),
.io_aqspi_miso(`AQSPI_MISO(0)),
.io_aqspi_isDirIn(),
.io_aqspi_csn(`AQSPI_CSN(0)),
.io_isSoftReset(isSoftReset[0]),
.io_interrupt(io_int_sig[0]),
.io_latchPin_0(latch0),
@@ -375,6 +379,11 @@ initial begin
#8000000000000
#8000000000000
`ifdef USING_OSPI
#8000000000000
#8000000000000
`endif
$display("Time Out !!!");
$fclose(spidata_file);
//$stop;
@@ -599,7 +608,23 @@ always @(posedge sck) begin
end else begin
bitCnt <= bitCnt + 1;
end
if ( idx >= (`ALL_DEV_NUM * 3) ) begin
if( &bitCnt ) begin
byteCnt <= byteCnt +1;
transCnt <= transCnt + 1;
if( (txBuf[2] & 8'h80) === 8'h80 & nextByteCnt >= 5) begin
rxBuf[byteCnt] <= exChangeRegi;
//$display("spi read out %x", exChangeRegi);
end
if( (txBuf[2] & 8'h80) === 8'h80 & nextByteCnt >= 4) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end else begin
exChangeRegi <= 0;
end
end else begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end
end else begin
if( &bitCnt ) begin
byteCnt <= byteCnt +1;
transCnt <= transCnt + 1;
@@ -615,6 +640,7 @@ always @(posedge sck) begin
end else begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end
end
end else begin
isBusy <= #500000 1'b0;
spi_csn[idx] <= #500000 1'b1;
@@ -631,9 +657,15 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, i
begin
txBuf[0] <= saddress[15:8];
txBuf[1] <= saddress[7:0];
if (sidx >=(`ALL_DEV_NUM * 3)) begin
txBuf[2] <= (scmd | slength[12:8]);
txBuf[3] <= slength[7:0];
length <= slength + 4;
end else begin
txBuf[2] <= scmd;
length <= slength + 3;
end
idx <= sidx;
#500000
@@ -645,9 +677,17 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, i
@( negedge isBusy) #100000000
begin
//$fwrite(spidata_file, "------------%5t------------\n", $realtime);
$fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
$realtime, ((sidx >= `ALL_DEV_NUM)? ((sidx >= (`ALL_DEV_NUM * 2))? (sidx - (`ALL_DEV_NUM * 2)):(sidx - `ALL_DEV_NUM)):sidx), txBuf[0], txBuf[1],
((txBuf[2] == 0)? "Write":" Read"), slength);
$fwrite(spidata_file, "T:%t \tdev:%4d(%4d), addr:0x%02h%02h, %s, len:%4d (0x%02h%02h)\n",
$realtime,
sidx % (`ALL_DEV_NUM), sidx,
txBuf[0],
txBuf[1],
(((txBuf[2] & 8'h80) == 0)? "Write":" Read"),
slength,
txBuf[2], txBuf[3]);
if (sidx >=(`ALL_DEV_NUM * 3)) begin _pos = 4; end
else begin _pos = 3; end
if ( ((saddress == 16'h0800)
|| (saddress == 16'h1000)
@@ -656,9 +696,15 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, i
|| (saddress == 16'h2800)
|| (saddress == 16'h3000)
|| (saddress == 16'h3800)
|| (saddress == 16'h4000))
&& ((sidx == 0) || (sidx == `ALL_DEV_NUM) || (sidx == (`ALL_DEV_NUM * 2)))) begin
_pos = 3;
|| (saddress == 16'h4000)
)
&& ((sidx == 0)
|| (sidx == `ALL_DEV_NUM)
|| (sidx == (`ALL_DEV_NUM * 2))
|| (sidx == (`ALL_DEV_NUM * 3))
)
) begin
for (integer _k = 0; _k < 4; _k++) begin
if (scmd == 0) begin
$fwrite(spidata_file, "%02h ", txBuf[_k + _pos]);
@@ -741,9 +787,9 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength, i
end else begin
for (integer i=0; i<slength; i++) begin
if (scmd == 0) begin
$fwrite(spidata_file, "%02h ", txBuf[i + 3]);
$fwrite(spidata_file, "%02h ", txBuf[i + _pos]);
end else begin
$fwrite(spidata_file, "%02h ", rxBuf[i + 3]);
$fwrite(spidata_file, "%02h ", rxBuf[i + _pos]);
end
c_line = 0;
if ((i+1)%16 == 0) begin
@@ -820,12 +866,35 @@ always @(negedge io_int_sig[4]) begin
$fdisplay(spidata_file, "**SLV3 INT CLEAR: %t", $realtime);
end
//`define USING_IQSPI
//`define USING_OSPI
//`define USING_OQSPI
//`define USING_AQSPI
`ifdef USING_IQSPI
`define INTERFACE_IDX 0//internal spi
`define ARRAY_IDX_OFF 3
`endif
`ifdef USING_OSPI
`define INTERFACE_IDX (`ALL_DEV_NUM)//internal spi
`define ARRAY_IDX_OFF 3
`endif
`ifdef USING_OQSPI
`define INTERFACE_IDX (`ALL_DEV_NUM * 2)//internal spi
`define ARRAY_IDX_OFF 3
`endif
`ifdef USING_AQSPI
`define INTERFACE_IDX (`ALL_DEV_NUM * 3)//internal spi
`define ARRAY_IDX_OFF 4
`endif
`define INTERFACE_IDX 0 //internal spi
`define IF_IDX(idx) ((`INTERFACE_IDX)+(idx))
`define IF_IQSPI(idx) ((idx))
`define IF_OQSPI(idx) ((`ALL_DEV_NUM * 2) + (idx))
`define IF_AQSPI(idx) ((`ALL_DEV_NUM * 3) + (idx))
`define IF_OSPI(idx) ((`ALL_DEV_NUM) + (idx))
`define SPI_WRITE 8'h00
`define SPI_READ 8'h80
@@ -865,14 +934,14 @@ end
if (cmd == (`SPI_WRITE)) begin \
f_write(logh, addr, cmd, len);\
for (integer _k = 0; _k < len; _k++) begin \
$fwrite(logh, "8'h%02h ", txBuf[3 + _k]); \
$fwrite(logh, "8'h%02h ", txBuf[`ARRAY_IDX_OFF + _k]); \
end \
spi_trans(addr, cmd, len, iface); \
end else begin \
spi_trans(addr, cmd, len, iface); \
f_write(logh, addr, cmd, len);\
for (integer _k = 0; _k < len; _k++) begin \
$fwrite(logh, "8'h%02h ", rxBuf[3 + _k]); \
$fwrite(logh, "8'h%02h ", rxBuf[`ARRAY_IDX_OFF + _k]); \
end \
end \
$fwrite(logh, "\n")
@@ -892,37 +961,22 @@ task wait_comm_finished(input [16:0] dev_idx);
st = $realtime;
is_run = 1;
`ifdef enable_wait_clear_int
txBuf[0] = 8'h00;
txBuf[1] = 8'h78;
txBuf[2] = `SPI_WRITE;
txBuf[3] = 8'h03;
txBuf[4] = 8'h00;
txBuf[5] = 8'h00;
txBuf[6] = 8'h00;
length = 8'h07;
idx = `IF_IQSPI(dev_idx);
#500000
@(negedge sck)
isReq <= 1;
@(posedge sck) #500000
isReq <= 0;
@( negedge isBusy) #100000000
begin
end
`endif
while (is_run == 1) begin
txBuf[0] = 8'h00;
txBuf[1] = 8'h74;
txBuf[2] = `SPI_READ;
if (dev_idx >=(`ALL_DEV_NUM * 3)) begin
txBuf[2] <= (`SPI_READ | 8'h0);
txBuf[3] <= 8'h04;
length = 8'h08;
//$display("using AQspi");
end else begin
txBuf[2] <= `SPI_READ;
length = 8'h07;
idx = `IF_IQSPI(dev_idx);
//$display("using iqspi");
end
idx = dev_idx;
#500000
@(negedge sck)
@@ -936,11 +990,11 @@ task wait_comm_finished(input [16:0] dev_idx);
end
#100000000
//$display("%x %x", rxBuf[3], rxBuf[6]);
if ((rxBuf[3] & 8'h02) == 8'h02)
if ((rxBuf[`ARRAY_IDX_OFF] & 8'h02) == 8'h02)
begin
is_run = 0;
end
if ((rxBuf[6] & 8'h60) != 8'h00)
if ((rxBuf[`ARRAY_IDX_OFF+3] & 8'h60) != 8'h00)
begin
$display("error occur");
is_run = 0;
@@ -959,154 +1013,6 @@ initial begin
#50000000
`ifdef ENABLE_REG_RW1_TEST
/*---------------------------------------------------------------------------------------------------------
测试用例
1. 从IP中读取寄存器，上电后的寄存器期望值为0
---------------------------------------------------------------------------------------------------------*/
begin:READ_REG_TESTCASE
`BEGIN_TESTCASE(`ENABLE_REG_RW1_TEST);
_t_start = $realtime;
$fdisplay(spidata_file, "测试用例：从IP中读取寄存器，上电后的寄存器期望值为0");
`SPI_TRANS( (16'h00), (`SPI_READ), (64), (`IF_OSPI(0)) );
`SPI_TRANS( (16'h00), (`SPI_READ), (64), (`IF_OSPI(1)) );
`SPI_TRANS( (16'h00), (`SPI_READ), (64), (`IF_OSPI(2)) );
`SPI_TRANS( (16'h00), (`SPI_READ), (64), (`IF_OSPI(3)) );
`SPI_TRANS( (16'h00), (`SPI_READ), (64), (`IF_OSPI(4)) );
_t_end = $realtime;
$fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start);
`END_TESTCASE(`ENABLE_REG_RW1_TEST);
end
`endif
begin:SETTING_INTERFACE
if ((`INTERFACE_IDX) == `ALL_DEV_NUM) begin
$fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的SPI接口访问EasyBus");
txBuf[0+3] = 8'h01;
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(0)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(1)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(2)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(3)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(4)) );
end else if ((`INTERFACE_IDX) == (`ALL_DEV_NUM * 2)) begin
$fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的QSPI接口访问EasyBus");
txBuf[0+3] = 8'h02;
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(0)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(1)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(2)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(3)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(4)) );
end else begin
$fdisplay(spidata_file, "\n\n从内部QSPI接口访问EasyBus");
txBuf[0+3] = 8'h00;
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(0)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(1)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(2)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(3)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_OSPI(4)) );
end
end
`ifdef ENABLE_INT_INIT_TEST
begin:CHECK_INTERRUPT_SIG
$fdisplay(spidata_file, "\n\n测试用例：检查设备的INTERRUPT信号");
@(posedge clock) begin
if (io_int_sig[0]) $fdisplay(spidata_file, "**MST Interrupt.");
if (io_int_sig[1]) $fdisplay(spidata_file, "**SLV0 Interrupt.");
if (io_int_sig[2]) $fdisplay(spidata_file, "**SLV1 Interrupt.");
if (io_int_sig[3]) $fdisplay(spidata_file, "**SLV2 Interrupt.");
if (io_int_sig[4]) $fdisplay(spidata_file, "**SLV3 Interrupt.");
end
$fdisplay(spidata_file, "-检查中断");
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-清中断");
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'h00;
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h80;
spi_trans( (16'h78), (`SPI_WRITE), (4), (`IF_IDX(0)) );
spi_trans( (16'h78), (`SPI_WRITE), (4), (`IF_IDX(1)) );
spi_trans( (16'h78), (`SPI_WRITE), (4), (`IF_IDX(2)) );
spi_trans( (16'h78), (`SPI_WRITE), (4), (`IF_IDX(3)) );
spi_trans( (16'h78), (`SPI_WRITE), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-检查中断");
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(4)) );
end
begin:CHECK_INTERRUPT_CFG_REG
$fdisplay(spidata_file, "\n\n测试用例：检查设备的INTERRUPT信号设置寄存器");
$fdisplay(spidata_file, "-检查中断");
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-设置中断");
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'h00;
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-检查中断");
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-设置中断");
txBuf[0+3] = 8'h0F;
txBuf[1+3] = 8'h00;
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(0)) );
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'hFF;
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_WRITE), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-检查中断");
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(0)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(1)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(2)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(3)) );
spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(4)) );
$fdisplay(spidata_file, "-中断改为脉冲模式");
txBuf[3] = 8'h10;
txBuf[4] = 8'h8A;
spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(1)) );
spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(2)) );
spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(3)) );
spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(4)) );
end
`endif
`include "tc_runlist.vh"

8
tb/shinTest/gen_pkt.py
View File

@@ -23,7 +23,7 @@ if __name__ == '__main__':
environment.gen_slv_dev_num(4)
environment.bringup()
'''
#'''
add_tc_2_runlist(errorPkt.tc1())
add_tc_2_runlist(errorPkt.tc2())
add_tc_2_runlist(errorPkt.tc3())
@@ -64,7 +64,7 @@ if __name__ == '__main__':
add_tc_2_runlist(errorPkt.tc38())
#'''
'''
#'''
add_tc_2_runlist(rwregs.tc1())
add_tc_2_runlist(rwregs.tc2())
add_tc_2_runlist(rwregs.tc3())
@@ -108,13 +108,13 @@ if __name__ == '__main__':
add_tc_2_runlist(base.tc31())
#'''
'''
#'''
add_tc_2_runlist(broadcast.tc1())
add_tc_2_runlist(broadcast.tc2())
add_tc_2_runlist(broadcast.tc3())
#'''
'''
#'''
add_tc_2_runlist(sync.tc1())
add_tc_2_runlist(sync.tc2())
add_tc_2_runlist(sync.tc3())