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修改测试时钟偏差的仿真测试思路

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bacon
2025-09-22 15:39:22 +08:00
parent 5620be6b04
commit 8ed508f655
4 changed files with 109 additions and 251 deletions
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50
tb/shinTest/Makefile_vcs
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@@ -4,6 +4,7 @@ OUTPUT = shin_test
CPU_COUNT := $(shell nproc)
SPI_TYPE ?= -spi 0
TRANS_CODE ?=
DEVCLK ?= --dev1 0 90 --dev2 0 -90
VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
-full64 \
@@ -25,59 +26,12 @@ testShin_vcs:
python3 ./shinTest/check_testcase.py
testShinClk_vcs:
python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90
python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data1.txt
mv generated/wave.vcd generated/wave1.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 70 -180 -8b10b
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data2.txt
mv generated/wave.vcd generated/wave2.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 45 185 --dev3 25 -185
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data3.txt
mv generated/wave.vcd generated/wave3.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 60 186 --dev3 15 -186
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data4.txt
mv generated/wave.vcd generated/wave4.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 80 187 --dev2 30 -187
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data5.txt
mv generated/wave.vcd generated/wave5.vcd
\
python3 ./shinTest/gen_pkt_clk.py --dev1 70 188 --dev3 223 -188 -8b10b
mkdir -p generated/log
rm -rf generated/log/*
${VCS} -f ./shinTestClk_vcs.f
${SIM}
python3 ./shinTest/check_testcase.py
mv spi_trans_data.txt generated/spi_trans_data6.txt
mv generated/wave.vcd generated/wave6.vcd
testShinMany_vcs: