diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index fe3181c..a02f0b6 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -34,8 +34,8 @@ val reset_calib = Input(Bool())
   val crcErr         = Output(Bool())
   val linkErr        = Output(Bool())
 
-  val testFail = Output(Bool())
-  val testDone = Output(Bool())
+  // val interrupt = Output(Bool())
+
 }
 
 // class Master_Status_Bundle extends Bundle{
@@ -111,8 +111,6 @@ class BackBoardMstBase extends Module{ //10M
 
 
 trait BackBoardMstFSMC{ this: BackBoardMstBase =>
-  io.testDone := DontCare
-  io.testFail := DontCare
 
   val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
   val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
@@ -126,9 +124,9 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     val fsmcWRSync  = ShiftRegisters( ~io.FSMC.wrn,  3, false.B, true.B )
     val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )  
 
-    io.FSMC.ADOEn := fsmcRDSync(1) & fsmcCSSync(1) & ~fsmcADVSync(1)
+    io.FSMC.ADOEn := fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0)
 
-    val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )
+    val latchAddr = RegEnable( io.FSMC.ADIn, (~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) )
 
     val isAccessSRAM = ~latchAddr.extract(10) 
     val isAccessReg  =  latchAddr.extract(10)
@@ -142,11 +140,11 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
 
-    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(1) & fsmcWRSync(1) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
+    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
     mirrorDown.io.addrw  := activeAddr
     mirrorDown.io.dataw  := io.FSMC.ADIn
 
-    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(1) & fsmcRDSync(1) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
+    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
     mirrorUp.io.addrr  := activeAddr
 
 
@@ -176,19 +174,15 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     ))
 
 
-    val isNewWR = RegInit(false.B)
 
-    when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
-      isNewWR := true.B
+    when( isAccessReg & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
+      isRegRefleshFlip := ~isRegRefleshFlip
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn
 
     }
 
-    when( fsmcCSSync(2) & ~fsmcCSSync(1) & isNewWR ){
-      isNewWR := false.B
-      isRegRefleshFlip := ~isRegRefleshFlip
-    }
+
 
   }
 
@@ -255,10 +249,6 @@ trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
   mirrorUp.io.enr    := false.B
   mirrorUp.io.addrr  := 0.U
 
-  val testDone = RegInit(false.B)
-  val testFail = RegInit(false.B)
-  io.testDone := ~testDone
-  io.testFail := ~testFail
 }
 
 
@@ -354,11 +344,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
       when( lvdsMst.io.slave_link_num_valid ){
         when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
           stateCur := 7.U
-          // testDone := true.B
-          // testFail := false.B
         } .otherwise{
-          // testDone := false.B
-          // testFail := true.B
           printf("Initialization failed, waitting for timeout!\n")
         }
       }