拆分初始化，同步流程，交给软件控制

src/main/scala/backBoard/BackBoardMst.scala

@@ -34,23 +34,6 @@ val reset_calib = Input(Bool())
 
 }
 
-// class Master_Status_Bundle extends Bundle{
-//   val zero = UInt(11.W)
-//   val cdrErr         = Bool()
-//   val crcErr         = Bool()
-//   val linkErr        = Bool()
-//   val synchronize    = Bool()
-//   val initialization = Bool()
-// }
-
-// class Master_Control_Bundle extends Bundle{
-//   val zero = UInt(13.W)
-//   val transmit       = Bool()
-//   val synchronize    = Bool()
-//   val initialization = Bool()
-// }
-
-
 class BackBoardMstBase extends Module{ //10M
   val io: BackBoardMstIO = IO(new BackBoardMstIO)
 
@@ -73,6 +56,7 @@ class BackBoardMstBase extends Module{ //10M
 
   val slvNum  = RegInit(0.U(6.W))
   val slvOffLine = RegInit(0.U(6.W))
+  val linkNum = RegInit(0.U(7.W))
   val testReg = RegInit("haa55".U(16.W))
   val interrupt = RegInit(false.B); io.interrupt := interrupt
 
@@ -163,6 +147,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
       ( activeAddr === 2.U) -> slvNum,
       ( activeAddr === 3.U) -> slvOffLine,
       ( activeAddr === 4.U) -> testReg,
+      ( activeAddr === 5.U) -> linkNum,
     ))
 
 
@@ -265,15 +250,12 @@ with BackBoardMstFSMC
 }
 
 
-trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
+trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
-
-  val isInitCntReset = ( ~RegNext(ctrlInit) & ctrlInit ) | (stateCur === 3.U) | (stateCur === 8.U)
-  val ( _, isInitTimeout ) = Counter(Range( 0,5200), ctrlInit, isInitCntReset)
-  val synchCnt = Reg(UInt(3.W))
 
+  val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
 
   when(ctrlInit){
-    when( isInitTimeout ){
+    when( isInitStart ){
 
       stateCur := 0.U
 
@@ -302,104 +284,55 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
       tx_start := false.B
 
       when( lvdsMst.io.slave_link_num_valid ){
-        slvNum := lvdsMst.io.slave_link_num - 1.U
+        linkNum := lvdsMst.io.slave_link_num
         stateCur := 3.U
-      }
-
-    } .elsewhen( stateCur === 3.U ){
-      frame_info_update_en := false.B
-      slave_type_num       := 0.U
-      slave_data_length    := 0.U
-
-      tx_start := false.B
-
-      stateCur := 4.U
-      
-    } .elsewhen( stateCur === 4.U ){
-      stateCur := 5.U
-
-      frame_info_update_en := true.B
-      slave_type_num       := Cat( "b00".U(2.W), slvNum )
-      slave_data_length    := ((8/8)*32-1).U
-
-      tx_start := false.B
-    } .elsewhen( stateCur === 5.U ){ // tx start
-      stateCur := 6.U
-
-      frame_info_update_en := false.B
-      tx_start := true.B
-
-    } .elsewhen( stateCur === 6.U ){
-
-      tx_start := false.B
-
-      when( lvdsMst.io.slave_link_num_valid ){
-        when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
-          stateCur := 7.U
-        } .otherwise{
-          printf("Initialization failed, waitting for timeout!\n")
-        }
-      }
-
-    } .elsewhen( stateCur === 7.U ){
-      when( ctrlSynch ){
-        stateCur := 8.U
-        synchCnt := 0.U
-      } .otherwise{
-        stateCur := 14.U
         statusInit  := true.B
         ctrlInit    := false.B
         interrupt   := true.B
       }
 
-    } .elsewhen( stateCur === 8.U ){   //synch
+    } .elsewhen( stateCur === 3.U ){
+
+    }
+  }
+}
+
+trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
+  val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch
+
+  when( ctrlSynch ){
+    when( isSyncStart ){
+      stateCur := 0.U
       frame_info_update_en := false.B
       slave_type_num       := 0.U
       slave_data_length    := 0.U
-
       tx_start := false.B
-
+    }.elsewhen( stateCur === 0.U ){
-      stateCur := 9.U
+      stateCur := 1.U
-      
-    } .elsewhen( stateCur === 9.U ){
-      stateCur := 10.U
 
       frame_info_update_en := true.B
       slave_type_num       := Cat( "b01".U(2.W), slvNum )
       slave_data_length    := ((8/8)*32-1).U
 
       tx_start := false.B
-    } .elsewhen( stateCur === 10.U ){ // tx start
+    } .elsewhen( stateCur === 1.U ){ // tx start
-      stateCur := 11.U
+      stateCur := 2.U
 
       frame_info_update_en := false.B
       tx_start := true.B
 
-    } .elsewhen( stateCur === 11.U ){
+    } .elsewhen( stateCur === 2.U ){
 
       tx_start := false.B
 
       when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
-        stateCur := 12.U
+        stateCur := 3.U
-        synchCnt := synchCnt + 1.U
-      }
-
-    } .elsewhen( stateCur === 12.U ){
-      when( synchCnt === 4.U ){
-        stateCur := 13.U
-      } .otherwise{
-        stateCur := 8.U
-      }
-    } .elsewhen( stateCur === 13.U ){
-      stateCur := 14.U
         statusSynch := true.B
-      statusInit  := true.B
         ctrlSynch   := false.B
-      ctrlInit    := false.B
         interrupt   := true.B
-    } .elsewhen( stateCur === 14.U ){
+      }
 
-    } .elsewhen( stateCur === 15.U ){
+    } .elsewhen( stateCur === 3.U ){
 
     }
     .otherwise{
@@ -407,17 +340,15 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
     }
   }
 
-
-
 }
 
 
 trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
 
-  val trigger = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
+  val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
 
   when(ctrlTransmit){
-    when( trigger ){  //reset
+    when( isTransStart ){  //reset
       stateCur := 0.U
 
       frame_info_update_en := false.B
@@ -462,14 +393,14 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
   val addrr = RegInit(0.U(11.W))
   val addrw = RegInit(0.U(11.W))
 
-  when( trigger ){
+  when( isTransStart ){
     addrw := 0.U
   } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
     assert( (stateCur === 2.U) || (stateCur === 3.U) )
     addrw := addrw + 1.U
   }
 
-  when( trigger ){
+  when( isTransStart ){
     addrr := 0.U
   } .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){
     addrr := addrr + 1.U
@@ -505,6 +436,7 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
 }
 
 class BackBoardMst extends BackBoardMstLVDSBase
-with BackBoardMstLVDSInitialization
+with BackBoardMstLVDSInit
+with BackBoardMstLVDSSync
 with BackBoardMstLVDSTransmit
 with BackBoardMstLVDSError