From 8a9aa0436cdbc8c2733fdfccd4fcb249a3958bcf Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 19 Sep 2023 18:03:30 +0800 Subject: [PATCH] a sign for tx/rx clock merge --- src/main/scala/mac/MAC.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala index 68a253b..1e3afc8 100644 --- a/src/main/scala/mac/MAC.scala +++ b/src/main/scala/mac/MAC.scala @@ -67,6 +67,8 @@ class MacIO extends Bundle with MDIO{ val mcrs_pad_i = Input(Bool()) // val int_o = Output(Bool()) + + val isLoopBack = Output(Bool()) } class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{ @@ -492,7 +494,9 @@ dontTouch(Collision ) dontTouch(CarrierSense_Tx2) dontTouch(RxEnSync ) -printf("Warning! clock doesn't switch when loopBck!") + +io.isLoopBack := r_LoopBck + // Muxed MII receive data valid MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync)