ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

硬件中断使能时钟为高

Browse Source
This commit is contained in:
Ruige Lee
2025-08-06 11:42:59 +08:00
committed by bacon
parent 41b83b83bc
commit 8a41553aea
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -953,8 +953,10 @@ trait InterfaceSystem{ this: InterfaceBase =>
cReg.intEnable :=
Cat(
1.U(1.W), //复位中断，时钟为1
RegEnable( dataw(6,0), 0.U, isEnW & addrw === "h73".U ),
1.U(1.W), //复位中断，时钟为1 //31 上电复位
1.U(1.W), //复位中断，时钟为1 //30 上行硬件错误
1.U(1.W), //复位中断，时钟为1 //29 下行硬件错误
RegEnable( dataw(4,0), 0.U, isEnW & addrw === "h73".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h72".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ),