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低地址位宽推断错误修复

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This commit is contained in:
Ruige Lee
2025-05-27 15:25:46 +08:00
parent 8f5cc5c4e9
commit 88e65fb364
1 changed files with 25 additions and 31 deletions
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56
src/main/scala/backBoard/shin/Interface.scala
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@@ -225,7 +225,7 @@ abstract class InterfaceBase extends Module{
) ++
((0 until 6).map{ i =>
(addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
(addr === ("h2".U(16.W) + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
}) ++
Seq(
@@ -250,7 +250,7 @@ abstract class InterfaceBase extends Module{
((0 until 16).map{ i =>
(addr === ("h50".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
(addr === ("h50".U(16.W) + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
}) ++
Seq(
@@ -353,13 +353,13 @@ abstract class InterfaceBase extends Module{
(addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24),
) ++
( 0 until 128 ).map{ i =>
( addr === ("h180".U + i.U ) ) -> cReg.custom(i)
( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h302".U + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0)
} ++
( 0 until 8 ).map{ i =>
( addr === ("h303".U + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
( addr === ("h303".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(10,8)
} ++
Seq()
)
@@ -449,7 +449,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.hwSerial :=
Cat(
(0 until 6).map{ i =>
RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
}.reverse
)
@@ -459,7 +459,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.encryptKey :=
Cat(
(0 until 16).map{ i =>
RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U + i.U) & cReg.mstOrSlv === 0.U )
RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
}.reverse
)
@@ -470,7 +470,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
// mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
( 0 until 128 ).map{ i =>
cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U + i.U)) )
cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
}
@@ -489,9 +489,9 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}
for( i <- 0 until 4 ){
when( io.lvds.addrw === ("h122".U + (2*i).U)){
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
}
}
@@ -525,13 +525,13 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}
for( i <- 1 until 4 ){
when( addrw === ("h13c".U + (4*(i-1)).U) ){
when( addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,8), dataw )
} .elsewhen( addrw === ("h13d".U + (4*(i-1)).U) ){
} .elsewhen( addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) )
} .elsewhen( addrw === ("h13e".U + (4*(i-1)).U) ){
} .elsewhen( addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) )
} .elsewhen( addrw === ("h13f".U + (4*(i-1)).U) ){
} .elsewhen( addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) )
}
}
@@ -555,24 +555,18 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
for( i <- 0 until 8 ){
cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
when( isEnW & addrw === ("h303".U + (i*4).U) ){
when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
smTrigLen_H(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U + (i*4).U)){
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
smTrigLen_H(i) := io.lvds.dataw
}
when( isEnW & addrw === ("h302".U + (i*4).U) ){
when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
smTrigLen_L(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U + (i*4).U)){
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
smTrigLen_L(i) := io.lvds.dataw
}
// Cat(
// RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
// RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
// )
}
@@ -623,9 +617,9 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
}
for( i <- 0 until 4 ){
when( io.lvds.addrw === ("h122".U + (2*i).U)){
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
}
}
@@ -659,13 +653,13 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
}
for( i <- 1 until 4 ){
when( io.lvds.addrw === ("h13c".U + (4*(i-1)).U) ){
when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === ("h13d".U + (4*(i-1)).U) ){
} .elsewhen( io.lvds.addrw === ("h13d".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) )
} .elsewhen( io.lvds.addrw === ("h13e".U + (4*(i-1)).U) ){
} .elsewhen( io.lvds.addrw === ("h13e".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) )
} .elsewhen( io.lvds.addrw === ("h13f".U + (4*(i-1)).U) ){
} .elsewhen( io.lvds.addrw === ("h13f".U(16.W) + (4*(i-1)).U) ){
syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) )
}
}
@@ -709,7 +703,7 @@ trait InterfaceSync{ this: InterfaceBase =>
syncSign(i) := true.B
} .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){
syncSign(i) := false.B
} .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U + (2*i).U) ){
} .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U(16.W) + (2*i).U) ){
syncSign(i) := false.B
}