From 87f28c75b089dd7cd55bfaddc3725726495a3720 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 24 Sep 2024 11:19:36 +0800
Subject: [PATCH] =?UTF-8?q?=E5=9F=BA=E6=9C=AC=E7=A8=B3=E5=AE=9A=E4=BC=A0?=
 =?UTF-8?q?=E8=BE=93?=
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---
 src/main/verilog/CDRIn_fpga.v  | 47 ++++++++++++++++++++++++------
 src/main/verilog/CDROut_fpga.v | 52 ++++++++++++++++++++++++++++------
 2 files changed, 82 insertions(+), 17 deletions(-)

diff --git a/src/main/verilog/CDRIn_fpga.v b/src/main/verilog/CDRIn_fpga.v
index f2b4b4e..9d6ff5c 100644
--- a/src/main/verilog/CDRIn_fpga.v
+++ b/src/main/verilog/CDRIn_fpga.v
@@ -1,11 +1,40 @@
 module CDRIn_fpga(
     input clock,
-    input reset,
-    input overCLK,
-    input serDat,
 
-    output reg [7:0] led
 
+    output reg [7:0] led,
+//    input serDat
+    input  lvds_down_din_p,
+    input  lvds_down_din_n
+);
+
+wire resetn =1'b1;
+wire clk_400m;
+wire clk_100m;
+
+Gowin_PLLO Gowin_PLLO(
+  .lock(), 
+  .clkouta(clk_400m),
+  .clkin(clock)
+);
+
+wire serDat;
+
+
+TLVDS_IBUF lvds_downstream_in(
+  .O(serDat),
+  .I(lvds_down_din_p),
+  .IB(lvds_down_din_n)
+);
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (resetn),
+  .HCLKIN (clk_400m),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m)
 );
 
 
@@ -18,8 +47,8 @@ module CDRIn_fpga(
 
 
     CDRIn s_CDRIn(
-        .clock(clock),
-        .reset(reset),
+        .clock(clk_100m),
+        .reset(~resetn),
 
         .io_axis_ready(1'b1),
         .io_axis_valid(rx_axis_valid),
@@ -28,7 +57,7 @@ module CDRIn_fpga(
         .io_axis_bits_tuser(rx_axis_bits_tuser),
 
         .io_serDat(serDat),
-        .io_overCLK(overCLK)
+        .io_overCLK(clk_400m)
     );
 
 
@@ -36,7 +65,9 @@ module CDRIn_fpga(
     reg [7:0] led_temp;
     reg [7:0] cnt;
 
-    always @(posedge clock) begin
+
+
+    always @(posedge clk_100m) begin
         if ( rx_axis_valid & 1'b1 ) begin
             if ( cnt == 0 ) begin
                 led_temp <= rx_axis_bits_tdata;
diff --git a/src/main/verilog/CDROut_fpga.v b/src/main/verilog/CDROut_fpga.v
index aacb368..d757f08 100644
--- a/src/main/verilog/CDROut_fpga.v
+++ b/src/main/verilog/CDROut_fpga.v
@@ -1,13 +1,47 @@
 module CDROut_fpga(
     input clock, // 100MHZ
-    input reset,
-
-    output serDat
+    input resetn,
 
+//    output serDat
+  output lvds_down_dout_p,
+  output lvds_down_dout_n
 
 
 );
 
+
+wire clk_400m;
+wire clk_100m;
+wire serDat;
+
+
+Gowin_PLLO Gowin_PLLO(
+    .lock(),
+    .clkouta(clk_400m),
+    .clkin(clock)
+);
+
+
+
+defparam Inst4_CLKDIVC.DIV_MODE="4";
+defparam Inst4_CLKDIVC.GSREN="false";
+CLKDIV Inst4_CLKDIVC(
+  .RESETN (resetn),
+  .HCLKIN (clk_400m),
+  .CALIB  (1'b0     ),
+  .CLKOUT (clk_100m)
+);
+
+
+
+TLVDS_OBUF lvds_downstream_out(
+  .O(lvds_down_dout_p),
+  .OB(lvds_down_dout_n),
+  .I(serDat)
+);
+
+
+
     wire      tx_axis_ready;
 
     reg       tx_axis_valid = 0;
@@ -17,8 +51,8 @@ module CDROut_fpga(
 
 
     CDROut s_CDROut(
-        .clock(clock),
-        .reset(reset),
+        .clock(clk_100m),
+        .reset(~resetn),
 
         .io_axis_ready(tx_axis_ready),
         .io_axis_valid(tx_axis_valid),
@@ -32,8 +66,8 @@ module CDROut_fpga(
 
 
     reg [31:0] rtc_cnt;
-    always @(posedge clock) begin
-        if( rtc_cnt > 5000000 ) begin
+    always @(posedge clk_100m) begin
+        if( rtc_cnt > 10000000 ) begin
             rtc_cnt <= #2 0;
         end else begin
             rtc_cnt <= #2 rtc_cnt + 1;
@@ -45,7 +79,7 @@ module CDROut_fpga(
     reg [7:0] led_state;
 
 
-    always @(posedge clock) begin
+    always @(posedge clk_100m) begin
         if( rtc_cnt == 0 ) begin
             cnt <= #2 0;
             
@@ -78,7 +112,7 @@ module CDROut_fpga(
                         end
                         
                         if( cnt == 8'd1 ) begin
-                            tx_axis_bits_tdata <= #2 8'h1;
+                            tx_axis_bits_tdata <= #2 8'd1;
                         end
                                      
                         if( cnt == 8'd2 ) begin