拆分读写访问地址线，以优化时序

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -20,7 +20,8 @@ class SSPIInterfaceIO extends Bundle{
 }
 
 class RegAccessInterfaceIO extends Bundle{
-  val addrSel = Output(UInt(16.W))
+  val addrw = Output(UInt(16.W))
+  val addrr = Output(UInt(16.W))
   val dataw   = Output( UInt(8.W) )
   val datar   = Input( UInt(8.W) )
   val isEnW   = Output(Bool())
@@ -50,7 +51,8 @@ abstract class SpiInterfaceBase extends Module{
 
 
 
-  val addrSel = Reg(UInt(16.W))
+  val addrw = Reg(UInt(16.W))
+  val addrr = Reg(UInt(16.W))
   val spiCmd  = Reg(UInt(8.W))
 
   val isSpiWrite = spiCmd === 0.U
@@ -65,8 +67,10 @@ abstract class SpiInterfaceBase extends Module{
              (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead  & byteSel >= 4.U)
   io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
   io.dataw := exRegi
-  io.addrSel :=
-    Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
+  io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
+  io.addrw := addrw
+  // io.addrSel :=
+  //   Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
   val readData = RegEnable(io.datar, io.isEnR)
   
 
@@ -81,17 +85,28 @@ abstract class SpiInterfaceBase extends Module{
 
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
-    addrSel := 0.U
+    addrw := 0.U
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
-    addrSel := exRegi
+    addrw := exRegi
   } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
-    addrSel := Cat(exRegi, addrSel(7,0))
+    addrw := Cat(exRegi, addrw(7,0))
   } .otherwise{ // byteSel > 1.U
     when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
-      addrSel := addrSel + 1.U
+      addrw := addrw + 1.U
     }
   }
 
+  when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
+    addrr := 0.U
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
+    addrr := exRegi
+  } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
+    addrr := Cat(exRegi, addrr(7,0))
+  } .otherwise{ // byteSel > 1.U
+    when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
+      addrr := addrr + 1.U
+    }
+  }
 
   when( shiftCSn(2) & ~shiftCSn(1) ){  //CS下跳
     spiCmd  := "hFF".U