拆分读写访问地址线，以优化时序

2025-05-21 10:28:36 +08:00
parent d90ea07f5e
commit 8779d92790
4 changed files with 137 additions and 120 deletions
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -537,10 +537,11 @@ trait SlaveParserRW{ this: SlaveParserBase =>

    
  
-  io.lvds.addrSel := Mux1H(Seq(
-    isRead  -> addrr(10,0),
-    isWrite -> addrw(10,0),
-  ))
+
+  io.lvds.addrr := addrr(10,0)
+  io.lvds.addrw := addrw(10,0)
+
+
  assert( ~(isRead & isWrite) )