diff --git a/Makefile b/Makefile index 6c44975..85177f1 100644 --- a/Makefile +++ b/Makefile @@ -18,7 +18,8 @@ compile: mkdir -p ./generated/Rtpp cd ./rocket-chip/ && rm -f rocketchip.jar cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig - cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v + sed -e "s/CoreID = _RAND/\/\/CoreID = _RAND/g" ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v > ./generated/Rtpp/RtppConfig.v +# cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v # sbt "test:runMain test.testModule" @@ -54,6 +55,7 @@ VSimTop: +define+RANDOMIZE_INVALID_ASSIGN \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_DELAY=0 \ + +define+VERILATOR \ --exe --build \ ${PWD}/tb/verilator/sim_main.cpp \ -Mdir ./tb/build/ \ diff --git a/rocket-chip b/rocket-chip index 4543a40..917ac65 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit 4543a408ca691a3ba277d0c3a01611f3ceb92957 +Subproject commit 917ac659f02a9a0c9bfe736e7fa965d7692664cb diff --git a/tb/sw/src/mstSvr.S b/tb/sw/src/mstSvr.S index e40276e..d033f60 100644 --- a/tb/sw/src/mstSvr.S +++ b/tb/sw/src/mstSvr.S @@ -42,12 +42,6 @@ _prog_start: .balign 32 _rv32i_plic_handle: -#if 0 /*RV32的核心自动禁用中断,无需手动禁用*/ - csrr x16, mstatus # 读取 mstatus 寄存器 - andi x16, x16, ~(1 << 3) # 清除 MIE 位 (全局中断禁用) - csrw mstatus, x16 # 写回 mstatus 寄存器 -#endif - lw x23, 0(x17) # x23 = *plic_claim sw x23, 0(x17) # *plic_claim = x23 @@ -75,6 +69,9 @@ _rv32i_plic_handle: bne x23, x24, 4f #_if (x23 != x24) goto 4f sw x25, 0(x21) #_else #else + + + bne x23, x28, 1f #_if (x23 != x24) goto 1f sw x25, 0(x18) #_else j 4f @@ -92,11 +89,9 @@ _rv32i_plic_handle: 3: bne x23, x31, 4f #_if (x23 != x24) goto 4f sw x25, 0(x21) #_else + + #endif + 4: -#if 0 /*RV32的核心自动启动中断,无需手动启用*/ - csrr x16, mstatus - ori x16, x16, 1<<3 - csrw mstatus, x16 -#endif mret