From 86fc61e0a48f092f2fc7c28bb73337ca14b6bb46 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 11 Aug 2025 16:54:18 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=A4=E7=BB=84=E5=AF=84?=
 =?UTF-8?q?=E5=AD=98=E5=99=A8?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 28 +++++++++++++++++++
 src/main/scala/backBoard/shin/ShinTop.scala   |  6 ++++
 2 files changed, 34 insertions(+)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index ec04f66..5233306 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -44,6 +44,9 @@ class CommonRegisterBundle extends Bundle{
 
   val uniCode = UInt(64.W)
 
+  val pllCtrl = UInt(32.W)
+  val xtal    = UInt(32.W)
+
   val softResetCode = Vec(4, UInt(8.W))
 
   val intEnable = UInt(32.W)
@@ -242,13 +245,24 @@ abstract class InterfaceBase extends Module{
         (addr === ("h10".U(16.W) + i.U) ) -> cReg.uniCode( 8*i+7,8*i+0 )
       }) ++
 
+
+
       Seq(
         (addr === "h8".U )  -> cReg.busRate( 7,0 ),
         (addr === "h9".U )  -> cReg.spiSel,
         (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex(7,0),
         (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),
+      ) ++
 
+      ((0 until 4).map{ i =>
+        (addr === ("h18".U(16.W) + i.U) ) -> cReg.pllCtrl( 8*i+7,8*i+0 )
+      }) ++
 
+      ((0 until 4).map{ i =>
+        (addr === ("h1c".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
+      }) ++
+
+      Seq(
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
                 //(addr === "h21".U & isMstMode) -> mReg.txLength,
 
@@ -602,6 +616,20 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
+  cReg.pllCtrl := 
+    Cat(
+      RegEnable( dataw, "b10000000".U, isEnW & addrw === "h1b".U ),
+      RegEnable( dataw, "b00000000".U, isEnW & addrw === "h1a".U ),
+      RegEnable( dataw, "b11000000".U, isEnW & addrw === "h19".U ),
+      RegEnable( dataw, "b01011101".U, isEnW & addrw === "h18".U )
+    )
+  
+  cReg.xtal :=
+    Cat(
+      0.U(16.W),
+      RegEnable( dataw, "b00000101".U, isEnW & addrw === "h1d".U ),
+      RegEnable( dataw, "b00010101".U, isEnW & addrw === "h1c".U )
+    )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 7ba2710..64a4445 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -32,6 +32,9 @@ class ShinTopIO extends Bundle{
   val latchPin = Input(Vec(2, Bool()))
   val hwSerial = Input(UInt(48.W))
   val uniCode = Input(UInt(64.W))
+
+  val pllCtrl = Output(UInt(32.W))
+  val xtal    = Output(UInt(12.W))
 }
 
 
@@ -80,6 +83,9 @@ abstract class ShinTopBase extends Module{
   io.iSync := interface.io.sync
   io.oSync := interface.io.sync
 
+  io.pllCtrl := interface.io.cReg.pllCtrl
+  io.xtal    := interface.io.cReg.xtal(11,0)
+
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },