tx 32转8 基本测试通过

src/main/scala/Switch/SwitchMux.scala

@@ -34,6 +34,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
   val rxBuff = Module(new RxBuff)
   rxBuff.io.enq <> io.rxEnq(0)
 
+
   val txBuff = Module(new TxBuff)
   txBuff.io.deq <> io.txDeq(0)
 
@@ -102,7 +103,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
   rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
   assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
 
-  rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid
+  rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid & stateCur === stateIdle
 
   when( io.dmaMst.A.fire ){
     dmaTxAValid := false.B

src/main/scala/Switch/TxBuff.scala

@@ -78,12 +78,24 @@ trait TxBuffEnq{ this: TxBuffBase =>
 }
 
 trait TxBuffDeq{ this: TxBuffBase =>
+  val isBusy = RegInit(false.B)
+
+  when( io.deq.req.fire ){
+    assert( ~isBusy )
+    isBusy := true.B
+  } .elsewhen(io.deq.resp.fire){
+    assert( isBusy )
+    isBusy := false.B
+  }
+
   io.deq.resp <> io.enq.resp
 
   io.deq.req.valid := deqReqValid
   io.deq.req.bits  := reqInfo
 
-  io.deq.data <> buff.io.deq
+  io.deq.data.bits := buff.io.deq.bits
+  io.deq.data.valid := buff.io.deq.valid & isBusy
+  buff.io.deq.ready := io.deq.data.ready & isBusy
 
 }
 

src/main/scala/Switch/mac/MAC.scala

@@ -693,7 +693,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   macstatus.io.StatePreamble       := StatePreamble
   macstatus.io.StateData           := StateData
   macstatus.io.CarrierSense        := CarrierSense_Tx2
-  macstatus.io.TxUsedData          := TxUsedDataIn
   macstatus.io.Loopback            := r_LoopBck
   macstatus.io.r_FullD             := r_FullD
   macstatus.io.RstDeferLatched     := RstDeferLatched
@@ -737,7 +736,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
 
 
-  val txReq_ToAsync = Wire(new AsyncBundle(UInt(8.W)))
+  val txReq_ToAsync = Wire(new AsyncBundle(new TxFifo_Stream_Bundle))
   // val txResp_ToAsync = Wire(new AsyncBundle(Bool()))
   // val fateTxRespPort = Wire( Flipped(Decoupled(Bool())) )
   // fateTxReqPort.ready := true.B
@@ -758,12 +757,12 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
 
   withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
     macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
-    macTileLinkTx.io.TxStartFrm_sync            := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
+    // macTileLinkTx.io.TxStartFrm_sync            := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
     // macTileLinkTx.io.ReadTxDataFromFifo_syncb   := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)    
   }
 
 
-  wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B )
+  // wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B )
 
   RstDeferLatched := macTileLinkTx.io.RstDeferLatched
   TxStartFrm      := macTileLinkTx.io.TxStartFrm

src/main/scala/Switch/mac/MacStatus.scala

@@ -37,7 +37,6 @@ class MacStatusIO extends Bundle{
   val StatePreamble       = Input(Bool())
   val StateData           = Input(UInt(2.W))
   val CarrierSense        = Input(Bool())
-  val TxUsedData          = Input(Bool())
   val Loopback            = Input(Bool())
   val r_FullD             = Input(Bool())
   val RstDeferLatched     = Input(Bool())

src/main/scala/Switch/mac/MacTileLinkTx.scala

@@ -4,16 +4,22 @@ import chisel3._
 import chisel3.util._
 
 
+class TxFifo_Stream_Bundle extends Bundle{
+  val data = UInt(8.W)
+  val isStart = Bool()
+}
+
+
 class MacTileLinkTxIO extends Bundle{
 
-  val txReq  = Flipped(Decoupled(UInt(8.W)))
+  val txReq  = Flipped(Decoupled(new TxFifo_Stream_Bundle))
   // val txResp = Decoupled()
 
 
 
   val RstDeferLatched  = Output(Bool())
   val BlockingTxStatusWrite_sync = Input(Bool())
-  val TxStartFrm_sync            = Input(Bool())
+  // val TxStartFrm_sync            = Input(Bool())
 
   val TxStartFrm     = Output(Bool())     // Transmit packet start frame
   val TxEndFrm       = Output(Bool())     // Transmit packet end frame
@@ -61,9 +67,9 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
     Flop := ~Flop
   }
   
-  when(io.TxStartFrm_sync){
+  when( io.txReq.valid & io.txReq.bits.isStart ){
     TxStartFrm := true.B
-  } .elsewhen(TxUsedData_q | ~io.TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
+  } .elsewhen(TxUsedData_q | io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q) ){
     TxStartFrm := false.B
   }
 
@@ -95,11 +101,12 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
   // }
 
   io.txReq.ready := 
-    io.TxStartFrm_sync & ~TxStartFrm |
+      io.txReq.valid & io.txReq.bits.isStart & ~TxStartFrm |
       io.TxUsedData & Flop & ~LastWord |
       TxStartFrm & io.TxUsedData & Flop
 
-  TxData := io.txReq.bits
+
+  TxData := io.txReq.bits.data
 
   assert( ~(io.txReq.ready & ~io.txReq.valid) )
 

src/main/scala/Switch/mac/MacTilelink.scala

@@ -33,10 +33,10 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-    val txReq = Decoupled(UInt(8.W))
+    val txReq = Decoupled(new TxFifo_Stream_Bundle)
 
-    val TxStartFrm_wb = Output(Bool())
+    // val TxStartFrm_wb = Output(Bool())
-    val TxStartFrm_syncb = Input(Bool())
+    // val TxStartFrm_syncb = Input(Bool())
     val TxEndFrm_wb = Output(Bool())
 
     // val TxData_wb = Output(UInt(8.W))
@@ -137,7 +137,7 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  val TxStartFrm_wb = RegInit(false.B); io.TxStartFrm_wb := TxStartFrm_wb
+  val TxStartFrm_wb = RegInit(false.B); //io.TxStartFrm_wb := TxStartFrm_wb
   val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb
 
   val TxLength = RegInit(0.U(16.W))
@@ -154,7 +154,7 @@ abstract class MacTileLinkBase() extends Module{
 
   when( io.txDeq.req.fire ){
     TxStartFrm_wb := true.B
-  } .elsewhen(io.TxStartFrm_syncb){
+  } .elsewhen(io.txReq.fire){
     TxStartFrm_wb := false.B
   }
 
@@ -215,9 +215,12 @@ abstract class MacTileLinkBase() extends Module{
 
 
   // io.TxData_wb       := io.txDeq.data.bits
-  io.txReq <> io.txDeq.data
+  io.txReq.bits.data    := io.txDeq.data.bits
+  io.txReq.bits.isStart := TxStartFrm_wb
+  io.txReq.valid        := io.txDeq.data.valid
+  io.txDeq.data.ready   := io.txReq.ready
   // io.txDeq.data.ready    := ReadTxDataFromFifoSyncPluse
-  assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )
+  // assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )