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tx 32转8 基本测试通过

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RuigeLee
2023-10-24 14:00:51 +08:00
parent 54991d8cb5
commit 86fb086bd2
6 changed files with 43 additions and 22 deletions
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3
src/main/scala/Switch/SwitchMux.scala
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@@ -34,6 +34,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
val rxBuff = Module(new RxBuff)
rxBuff.io.enq <> io.rxEnq(0)
val txBuff = Module(new TxBuff)
txBuff.io.deq <> io.txDeq(0)
@@ -102,7 +103,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid
rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid & stateCur === stateIdle
when( io.dmaMst.A.fire ){
dmaTxAValid := false.B