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Merge branch 'ebmmu' into eb_dev

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This commit is contained in:
bacon
2025-06-24 17:26:09 +08:00
parent d79e712056 a7f27f5bf0
commit 86ba2d05b8
3 changed files with 372 additions and 280 deletions
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456
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -16,12 +16,15 @@ class SubMsgHeader extends Bundle{
val address = UInt(16.W) //子报文地址 val address = UInt(16.W) //子报文地址
val operator = UInt(4.W) //子报文命令类型 val operator = UInt(4.W) //子报文命令类型
val length = UInt(12.W) //子报文负载长度 val length = UInt(12.W) //子报文负载长度
val workCnt = UInt(16.W) //子报文工作计数
def isSeqIndex = style === 0.U def isSeqIndex = style === 0.U
def isLgcIndex = style === 2.U def isLgcIndex = style === 2.U
} }
class SubMsgTail extends Bundle{
val workCnt = UInt(16.W) //子报文工作计数
}
// class ShareSRAMIO extends Bundle{ // class ShareSRAMIO extends Bundle{
@@ -98,11 +101,12 @@ abstract class SlaveParserBase extends Module{
val STATE_IDLE = 0.U //空闲 val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U //子报文头 val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_DATA = 3.U //子报文数据 val STATE_PAYLOAD_DATA = 3.U //子报文数据
val STATE_CRC = 4.U //CRC校验 val STATE_SUBMSG_TAIL = 4.U
val STATE_ERROR = 5.U // val STATE_CRC = 5.U //CRC校验
val STATE_WAIT = 6.U val STATE_ERROR = 6.U //
val STATE_WAIT = 7.U
@@ -115,9 +119,7 @@ abstract class SlaveParserBase extends Module{
val isAckProbe = RegInit(false.B) val isAckProbe = RegInit(false.B)
val isLastDevice: Bool = RegInit(true.B) val isLastDevice: Bool = RegInit(true.B)
// val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft
// val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify
// val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev
io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U ) io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U )
val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify
val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev
@@ -172,18 +174,21 @@ abstract class SlaveParserBase extends Module{
//////////////////////////////////////// ////////////////////////////////////////
//子报文 //子报文
val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } val isDownSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } val isUpSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
val isDownSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
val isUpSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
//接收子报文 //接收子报文
val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载 val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
@@ -195,37 +200,42 @@ abstract class SlaveParserBase extends Module{
//下行接收 //下行接收
when( downRecParser.io.subMsgReq.fire ){ when( downRecParser.io.subMsgHeadReq.fire ){
when( isDownRecPing ){ when( isDownRecPing ){
downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex downSubMsgHeadInfo(0).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style downSubMsgHeadInfo(0).style := downRecParser.io.subMsgHeadReq.bits.style
downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address downSubMsgHeadInfo(0).address := downRecParser.io.subMsgHeadReq.bits.address
downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator downSubMsgHeadInfo(0).operator := downRecParser.io.subMsgHeadReq.bits.operator
downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length downSubMsgHeadInfo(0).length := downRecParser.io.subMsgHeadReq.bits.length
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt downSubMsgHeadInfo(0).source := 0.U
downSubMsgInfo(0).source := 0.U
} .otherwise{ //pong } .otherwise{ //pong
downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex downSubMsgHeadInfo(1).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style downSubMsgHeadInfo(1).style := downRecParser.io.subMsgHeadReq.bits.style
downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address downSubMsgHeadInfo(1).address := downRecParser.io.subMsgHeadReq.bits.address
downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator downSubMsgHeadInfo(1).operator := downRecParser.io.subMsgHeadReq.bits.operator
downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length downSubMsgHeadInfo(1).length := downRecParser.io.subMsgHeadReq.bits.length
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt downSubMsgHeadInfo(1).source := 1.U
downSubMsgInfo(1).source := 1.U }
}
when( downRecParser.io.subMsgTailReq.fire ){
when( isDownRecPing ){
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
} .otherwise{ //pong
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
} }
} }
when( ~isDownRecPing ){ //req fire 后 已经反相 when( isDownRecPing ){ //req fire 后
downRecFifo(0).io.enq.valid := downRecParser.io.data.valid downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
downRecFifo(0).io.enq.bits := downRecParser.io.data.bits downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
downRecParser.io.data.ready := downRecFifo(0).io.enq.ready downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
downRecFifo(1).io.enq.valid := false.B downRecFifo(1).io.enq.valid := false.B
downRecFifo(1).io.enq.bits := 0.U downRecFifo(1).io.enq.bits := 0.U
} .otherwise{ } .otherwise{
downRecFifo(0).io.enq.valid := false.B downRecFifo(0).io.enq.valid := false.B
downRecFifo(0).io.enq.bits := 0.U downRecFifo(0).io.enq.bits := 0.U
@@ -240,27 +250,31 @@ abstract class SlaveParserBase extends Module{
//上行接收 //上行接收
when( upRecParser.io.subMsgReq.fire ){ when( upRecParser.io.subMsgHeadReq.fire ){
when( isUpRecPing ){ when( isUpRecPing ){
upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex upSubMsgHeadInfo(0).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style upSubMsgHeadInfo(0).style := upRecParser.io.subMsgHeadReq.bits.style
upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address upSubMsgHeadInfo(0).address := upRecParser.io.subMsgHeadReq.bits.address
upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator upSubMsgHeadInfo(0).operator := upRecParser.io.subMsgHeadReq.bits.operator
upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length upSubMsgHeadInfo(0).length := upRecParser.io.subMsgHeadReq.bits.length
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt upSubMsgHeadInfo(0).source := 0.U
upSubMsgInfo(0).source := 0.U
} .otherwise{ } .otherwise{
upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex upSubMsgHeadInfo(1).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style upSubMsgHeadInfo(1).style := upRecParser.io.subMsgHeadReq.bits.style
upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address upSubMsgHeadInfo(1).address := upRecParser.io.subMsgHeadReq.bits.address
upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator upSubMsgHeadInfo(1).operator := upRecParser.io.subMsgHeadReq.bits.operator
upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length upSubMsgHeadInfo(1).length := upRecParser.io.subMsgHeadReq.bits.length
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt upSubMsgHeadInfo(1).source := 1.U
upSubMsgInfo(1).source := 1.U
} }
} }
when( upRecParser.io.subMsgTailReq.fire ){
when( isUpRecPing ){
upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
} .otherwise{
upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
}
}
@@ -274,71 +288,106 @@ abstract class SlaveParserBase extends Module{
downSendGen.io.subMsgReq.valid := downSendGen.io.subMsgHeadReq.valid :=
( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1)) ( isDownSendPing & isDownSubMsgHeadValid(0) ) | (~isDownSendPing & isDownSubMsgHeadValid(1))
downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) ) downSendGen.io.subMsgHeadReq.bits := Mux( isDownSendPing, downSubMsgHeadInfo(0), downSubMsgHeadInfo(1) )
when( downSendGen.io.subMsgReq.fire ){ //ready downSendGen.io.subMsgTailReq.valid :=
isDownSendPing := ~isDownSendPing ( isDownSendPing & isDownSubMsgTailValid(0) ) | ( ~isDownSendPing & isDownSubMsgTailValid(1))
downSendGen.io.subMsgTailReq.bits := Mux( isDownSendPing, downSubMsgTailInfo(0), downSubMsgTailInfo(1) )
when( downSendGen.io.subMsgHeadReq.fire ){ //ready
when( isDownSendPing ){ when( isDownSendPing ){
assert( isDownSubMsgValid(0) ) assert( isDownSubMsgHeadValid(0) )
isDownSubMsgValid(0) := false.B isDownSubMsgHeadValid(0) := false.B
} .otherwise{ } .otherwise{
assert( isDownSubMsgValid(1) ) assert( isDownSubMsgHeadValid(1) )
isDownSubMsgValid(1) := false.B isDownSubMsgHeadValid(1) := false.B
} }
} .elsewhen( downRecParser.io.subMsgReq.fire ){ } .elsewhen( downRecParser.io.subMsgHeadReq.fire ){
isDownRecPing := ~isDownRecPing
when( isDownRecPing ){ when( isDownRecPing ){
assert( ~isDownSubMsgValid(0) ) assert( ~isDownSubMsgHeadValid(0) )
isDownSubMsgValid(0) := true.B isDownSubMsgHeadValid(0) := true.B
} .otherwise{ } .otherwise{
assert( ~isDownSubMsgValid(1) ) assert( ~isDownSubMsgHeadValid(1) )
isDownSubMsgValid(1) := true.B isDownSubMsgHeadValid(1) := true.B
} }
} }
when( downSendGen.io.subMsgTailReq.fire ){
when( isDownSendPing ){
assert( isDownSubMsgTailValid(0) )
isDownSubMsgTailValid(0) := false.B
} .otherwise{
assert( isDownSubMsgTailValid(1) )
isDownSubMsgTailValid(1) := false.B
}
} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
when( isDownRecPing ){
assert( ~isDownSubMsgTailValid(0) )
isDownSubMsgTailValid(0) := true.B
} .otherwise{
assert( ~isDownSubMsgTailValid(1) )
isDownSubMsgTailValid(1) := true.B
}
}
when( downSendGen.io.subMsgTailReq.fire ){ //ready
isDownSendPing := ~isDownSendPing
} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
isDownRecPing := ~isDownRecPing
}
downRecFifo(0).io.deq <> downSendGen.io.data(0) downRecFifo(0).io.deq <> downSendGen.io.data(0)
downRecFifo(1).io.deq <> downSendGen.io.data(1) downRecFifo(1).io.deq <> downSendGen.io.data(1)
downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1))
//子报文上行发送 //子报文上行发送
upSendGen.io.subMsgReq.valid := upSendGen.io.subMsgHeadReq.valid :=
( isUpSendPing & isUpSubMsgValid(0) ) | ( isUpSendPing & isUpSubMsgHeadValid(0) ) |
( ~isUpSendPing & isUpSubMsgValid(1) ) ( ~isUpSendPing & isUpSubMsgHeadValid(1) )
upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) ) upSendGen.io.subMsgHeadReq.bits := Mux( isUpSendPing, upSubMsgHeadInfo(0), upSubMsgHeadInfo(1) )
when( upSendGen.io.subMsgReq.fire ){ //ready upSendGen.io.subMsgTailReq.valid :=
isUpSendPing := ~isUpSendPing ( isUpSendPing & isUpSubMsgTailValid(0) ) |
( ~isUpSendPing & isUpSubMsgTailValid(1) )
upSendGen.io.subMsgTailReq.bits := Mux( isUpSendPing, upSubMsgTailInfo(0), upSubMsgTailInfo(1) )
when( upSendGen.io.subMsgHeadReq.fire ){ //ready
when( isUpSendPing ){ when( isUpSendPing ){
assert( isUpSubMsgValid(0) ) assert( isUpSubMsgHeadValid(0) )
isUpSubMsgValid(0) := false.B isUpSubMsgHeadValid(0) := false.B
} .otherwise{ } .otherwise{
assert( isUpSubMsgValid(1) ) assert( isUpSubMsgHeadValid(1) )
isUpSubMsgValid(1) := false.B isUpSubMsgHeadValid(1) := false.B
} }
}.elsewhen( upRecParser.io.subMsgReq.fire ){ }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){
isUpRecPing := ~isUpRecPing
when( isUpRecPing ){ when( isUpRecPing ){
assert( ~isUpSubMsgValid(0) ) assert( ~isUpSubMsgHeadValid(0) )
isUpSubMsgValid(0) := true.B isUpSubMsgHeadValid(0) := true.B
} .otherwise{ } .otherwise{
assert( ~isUpSubMsgValid(1) ) assert( ~isUpSubMsgHeadValid(1) )
isUpSubMsgValid(1) := true.B isUpSubMsgHeadValid(1) := true.B
} }
} }
when( upSendGen.io.subMsgHeadReq.fire ){ //ready
isUpSendPing := ~isUpSendPing
}.elsewhen( upRecParser.io.subMsgHeadReq.fire ){
isUpRecPing := ~isUpRecPing
}
upRecFifo(0).io.deq <> upSendGen.io.data(0) upRecFifo(0).io.deq <> upSendGen.io.data(0)
upRecFifo(1).io.deq <> upSendGen.io.data(1) upRecFifo(1).io.deq <> upSendGen.io.data(1)
upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1))
} }
@@ -357,22 +406,40 @@ abstract class SlaveParserBase extends Module{
trait SlaveParserIndex{ this: SlaveParserBase => trait SlaveParserIndex{ this: SlaveParserBase =>
//下行接收 //下行接收
when( downRecParser.io.subMsgReq.fire & when( downRecParser.io.subMsgTailReq.fire ){
downRecParser.io.subMsgReq.bits.devIndex === 0.U & when( isDownRecPing &
downRecParser.io.subMsgReq.bits.style === 0.U & downSubMsgHeadInfo(0).devIndex === 0.U &
downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址 downSubMsgHeadInfo(0).style === 0.U &
localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_INDEX
indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U) ){
when( isDownRecPing ){ localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
} .otherwise{ //pong downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U } .elsewhen( ~isDownRecPing &
downSubMsgHeadInfo(1).devIndex === 0.U &
downSubMsgHeadInfo(1).style === 0.U &
downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_INDEX
){ //pong
localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} }
//上行接收 获取右侧索引号 // when( downRecParser.io.subMsgHeadReq.fire &
// downRecParser.io.subMsgHeadReq.bits.devIndex === 0.U &
// downRecParser.io.subMsgHeadReq.bits.style === 0.U &
// downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
// localDevIndex := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
// indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgHeadReq.bits.workCnt + 2.U)
// when( isDownRecPing ){
// downSubMsgHeadInfo(0).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
// } .otherwise{ //pong
// downSubMsgHeadInfo(1).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
// }
// }
} }
@@ -382,34 +449,27 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
trait SlaveParserRW{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase =>
// val isSeqIndexMatch = val isDownLgcWorked = RegInit(false.B)
// (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex) val isUpLgcWorked = RegInit(false.B)
// val downLgcAddress = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
// val isLgcIndexMatch =
// (downRecParser.io.subMsgReq.bits.isLgcIndex &
//下行接收 //下行接收
when( downRecParser.io.subMsgReq.fire ){ when( downRecParser.io.subMsgTailReq.fire ){
when( isDownRecPing ){ when( isDownRecPing ){
//override //override
when( when(
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & isDownLgcWorked ) ) ) |
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) { //自身包//写操作或读写操作) ) { //自身包//写操作或读写操作)
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} .otherwise{ //pong } .otherwise{ //pong
//override //override
when( when(
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE ) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & isDownLgcWorked ) ) ) |
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) { //自身包//写操作或读写操作 ) ) { //自身包//写操作或读写操作 )
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} }
} }
@@ -431,10 +491,10 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val downTransLenCnt = RegInit(0.U) val downTransLenCnt = RegInit(0.U)
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || ( downSubMsgInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || ( downSubMsgInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
) )
@@ -463,14 +523,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
downTransLenCnt := downTransLenCnt - 1.U downTransLenCnt := downTransLenCnt - 1.U
} }
when( downRecParser.io.subMsgTailReq.fire ){
isDownLgcWorked := false.B
} .elsewhen( isDownLgcAddrwAcquireTrans ){
isDownLgcWorked := true.B
}
//组合逻辑 //组合逻辑
when( downRecParser.io.subMsgReq.fire & ( when( downRecParser.io.subMsgHeadReq.fire & (
(downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex
)){//组合逻辑 )){//组合逻辑
logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address )
} .elsewhen( downRecParser.io.data.fire & ( } .elsewhen( downRecParser.io.data.fire & (
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(0).isLgcIndex ) | ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(1).isLgcIndex ) ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
)){//组合逻辑 )){//组合逻辑
logicAddrwNext := logicAddrw + 1.U logicAddrwNext := logicAddrw + 1.U
} .otherwise{//组合逻辑 } .otherwise{//组合逻辑
@@ -478,22 +544,22 @@ trait SlaveParserRW{ this: SlaveParserBase =>
} }
when( downRecParser.io.subMsgReq.fire ){ //子包头装填 when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填
when( when(
( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) |
( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
){ //常规寻址 ){ //常规寻址
addrw := downRecParser.io.subMsgReq.bits.address addrw := downRecParser.io.subMsgHeadReq.bits.address
} .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址 } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ //逻辑寻址
addrw := acquireDownPhyAddrw addrw := acquireDownPhyAddrw
} }
} .elsewhen( isWrite & downRecParser.io.data.fire ){ } .elsewhen( isWrite & downRecParser.io.data.fire ){
when( when(
( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) |
( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
){ ){
addrw := addrw + 1.U addrw := addrw + 1.U
} .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){
addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U )
} }
} }
@@ -524,24 +590,23 @@ trait SlaveParserRW{ this: SlaveParserBase =>
//上行接收 //上行接收
when( upRecParser.io.subMsgReq.fire ){ when( upRecParser.io.subMsgTailReq.fire ){
when( isUpRecPing ){ when( isUpRecPing ){
//override //override
when( when(
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
){ //自身包//读或读写 ){ //自身包//读或读写
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} .otherwise{ } .otherwise{
//override //override
when( when(
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
){ //自身包//读或读写 ) ){ //自身包//读或读写 )
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} }
} }
@@ -578,24 +643,30 @@ trait SlaveParserRW{ this: SlaveParserBase =>
) )
when( isUpLgcAddrrAcquireTrans & ( when( isUpLgcAddrrAcquireTrans & (
(upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
)){ //装填计数器 )){ //装填计数器
upTransLenCnt := acquireUpTransLen upTransLenCnt := acquireUpTransLen
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){
upTransLenCnt := upTransLenCnt - 1.U upTransLenCnt := upTransLenCnt - 1.U
} }
when( upRecParser.io.subMsgTailReq.fire ){
isUpLgcWorked := false.B
} .elsewhen( isUpLgcAddrrAcquireTrans ){
isUpLgcWorked := true.B
}
//组合逻辑 //组合逻辑
when( upRecParser.io.subMsgReq.fire & ( when( upRecParser.io.subMsgHeadReq.fire & (
(upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex
)){//组合逻辑 )){//组合逻辑
logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address )
} .elsewhen( upRecParser.io.data.fire){ } .elsewhen( upRecParser.io.data.fire){
when( when(
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex )
){//组合逻辑 ){//组合逻辑
logicAddrrNext := logicAddrr + 1.U logicAddrrNext := logicAddrr + 1.U
} .otherwise{ } .otherwise{
@@ -612,20 +683,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isRDSM5 = addrr(14,11) === "b0110".U val isRDSM5 = addrr(14,11) === "b0110".U
val isRDSM7 = addrr(14,11) === "b1000".U val isRDSM7 = addrr(14,11) === "b1000".U
val isSeqRead = val isSeqRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) )) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) )) | ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
) )
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
val isLgcRead = val isLgcRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
) )
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
@@ -633,54 +703,26 @@ trait SlaveParserRW{ this: SlaveParserBase =>
// when( upRecParser.io.subMsgReq.fire){
// when(
// ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
// ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
// ){
// addrr := upRecParser.io.subMsgReq.bits.address
// } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := acquireUpPhyAddrr
// }
// } .elsewhen( isUpLgcAddrrAcquireTrans ){
// when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := acquireUpPhyAddrr
// }
// }
// .elsewhen( isLvdsEnR ){
// assert(~isUpLgcAddrrAcquireTrans)
// when(
// ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
// ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
// ){
// addrr := addrr + 1.U
// } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
// }
// }
when( when(
((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | ((upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgHeadReq.bits.isSeqIndex & upRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex)) |
( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ( upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
){ ){
when( upRecParser.io.subMsgReq.fire){ when( upRecParser.io.subMsgHeadReq.fire){
addrr := upRecParser.io.subMsgReq.bits.address addrr := upRecParser.io.subMsgHeadReq.bits.address
} .elsewhen(isLvdsEnR){ } .elsewhen(isLvdsEnR){
addrr := addrr + 1.U addrr := addrr + 1.U
} }
} .elsewhen( isUpLgcAddrrAcquireTrans ){ } .elsewhen( isUpLgcAddrrAcquireTrans ){
when( when(
(upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
){ ){
addrr := acquireUpPhyAddrr addrr := acquireUpPhyAddrr
} }
} .elsewhen( isLvdsEnR & ( } .elsewhen( isLvdsEnR & (
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
)){ )){
assert(~isUpLgcAddrrAcquireTrans) assert(~isUpLgcAddrrAcquireTrans)
addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
@@ -701,8 +743,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
upRecFifo(0).io.enq.bits := upRecFifo(0).io.enq.bits :=
Mux( Mux(
( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, ( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) | (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, Mux( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
upRecParser.io.data.bits ) upRecParser.io.data.bits )
) )
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
@@ -716,8 +758,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
upRecFifo(1).io.enq.bits := upRecFifo(1).io.enq.bits :=
Mux( Mux(
( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, ( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) | (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, Mux( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
upRecParser.io.data.bits upRecParser.io.data.bits
) )
) )
@@ -765,18 +807,40 @@ trait SlaveParserRW{ this: SlaveParserBase =>
trait SlaveParserSync{ this: SlaveParserBase => trait SlaveParserSync{ this: SlaveParserBase =>
// when( upRecParser.io.subMsgTailReq.fire ){
// when( isUpRecPing ){
// //override
// when(
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
// ){ //自身包//读或读写
// upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
// }
// } .otherwise{
// //override
// when(
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
// ){ //自身包//读或读写 )
// upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
// }
// }
// }
//下行接收 //下行接收
when( downRecParser.io.subMsgReq.fire ){ when( downRecParser.io.subMsgTailReq.fire ){
when( isDownRecPing ){ when( isDownRecPing ){
//override //override
when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} .otherwise{ //pong } .otherwise{ //pong
//override //override
when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 )
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
} }
} }
} }
@@ -817,8 +881,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
//下行接收 //下行接收
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | ( ~isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ( isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
) )
val syncCnt = Reg(UInt(4.W)) val syncCnt = Reg(UInt(4.W))

109
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -13,7 +13,8 @@ class SlaveRecParserIO extends Bundle{
val stateCurr = Output(UInt(4.W)) val stateCurr = Output(UInt(4.W))
val frameReq = Valid( new FrameHeader ) val frameReq = Valid( new FrameHeader )
val subMsgReq = Valid( new SubMsgHeader ) val subMsgHeadReq = Valid( new SubMsgHeader )
val subMsgTailReq = Valid( new SubMsgTail )
val resp = Input(Bool()) val resp = Input(Bool())
val isError = Output(Bool()) val isError = Output(Bool())
@@ -30,9 +31,10 @@ class SlaveRecParser extends Module{
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_DATA = 3.U //子报文数据 val STATE_PAYLOAD_DATA = 3.U //子报文数据
val STATE_CRC = 4.U //CRC校验 val STATE_SUBMSG_TAIL = 4.U
val STATE_ERROR = 5.U // val STATE_CRC = 5.U //CRC校验
val STATE_WAIT = 6.U val STATE_ERROR = 6.U //
val STATE_WAIT = 7.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
@@ -44,7 +46,8 @@ class SlaveRecParser extends Module{
crc.io.isEnable := io.rec.fire & ( crc.io.isEnable := io.rec.fire & (
stateCurr === STATE_HEADER | stateCurr === STATE_HEADER |
stateCurr === STATE_SUBMSG_HEADER | stateCurr === STATE_SUBMSG_HEADER |
stateCurr === STATE_PAYLOAD_DATA stateCurr === STATE_PAYLOAD_DATA |
stateCurr === STATE_SUBMSG_TAIL
) )
@@ -72,22 +75,25 @@ class SlaveRecParser extends Module{
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
io.frameReq.valid := io.rec.fire & (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER) io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
val frameHeader = Reg(new FrameHeader) val frameHeader = Reg(new FrameHeader)
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := frameHeader.frameStyle io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
io.subMsgReq.valid := io.rec.fire & (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA) io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
val subMsgHeader = Reg(new SubMsgHeader) val subMsgHeader = Reg(new SubMsgHeader)
val subMsgTail = Reg(new SubMsgTail)
io.subMsgReq.bits.devIndex := subMsgHeader.devIndex io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
io.subMsgReq.bits.style := subMsgHeader.style io.subMsgHeadReq.bits.style := subMsgHeader.style
io.subMsgReq.bits.address := subMsgHeader.address io.subMsgHeadReq.bits.address := subMsgHeader.address
io.subMsgReq.bits.operator := subMsgHeader.operator io.subMsgHeadReq.bits.operator := subMsgHeader.operator
io.subMsgReq.bits.length := subMsgHeader.length io.subMsgHeadReq.bits.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
io.subMsgReq.bits.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
when( io.rec.fire ){ when( io.rec.fire ){
when( stateCurr =/= stateNext ){ when( stateCurr =/= stateNext ){
@@ -122,35 +128,43 @@ class SlaveRecParser extends Module{
when( io.rec.fire ){ when( io.rec.fire ){
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ when( stateCurr === STATE_HEADER ){
frameHeader.frameLenAim := io.rec.bits.tdata << 4 when( lengthCnt === 0.U ){
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){ frameHeader.frameLenAim := io.rec.bits.tdata << 4
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) } .elsewhen( lengthCnt === 1.U ){
frameHeader.frameStyle := io.rec.bits.tdata(1,0) frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){ frameHeader.frameStyle := io.rec.bits.tdata(1,0)
frameHeader.frameInfo := io.rec.bits.tdata << 8 } .elsewhen( lengthCnt === 2.U ){
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){ frameHeader.frameInfo := io.rec.bits.tdata << 8
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata } .elsewhen( lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
}
} }
when( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 0.U ){ when( stateCurr === STATE_SUBMSG_HEADER ){
subMsgHeader.devIndex := io.rec.bits.tdata << 6 when(lengthCnt === 0.U ){
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 1.U ){ subMsgHeader.devIndex := io.rec.bits.tdata << 6
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) } .elsewhen( lengthCnt === 1.U ){
subMsgHeader.style := io.rec.bits.tdata(1,0) subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 2.U ){ subMsgHeader.style := io.rec.bits.tdata(1,0)
subMsgHeader.address := io.rec.bits.tdata << 8 } .elsewhen( lengthCnt === 2.U ){
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 3.U ){ subMsgHeader.address := io.rec.bits.tdata << 8
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata } .elsewhen( lengthCnt === 3.U ){
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 4.U ){ subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
subMsgHeader.operator := io.rec.bits.tdata(7,4) } .elsewhen( lengthCnt === 4.U ){
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 subMsgHeader.operator := io.rec.bits.tdata(7,4)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 5.U ){ subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) } .elsewhen( lengthCnt === 5.U ){
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 6.U ){ subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8 }
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 7.U ){ }
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
when( stateCurr === STATE_SUBMSG_TAIL ){
when(lengthCnt === 0.U ){
subMsgTail.workCnt := io.rec.bits.tdata << 8
} .elsewhen( lengthCnt === 1.U ){
subMsgTail.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0)
}
} }
} }
@@ -173,14 +187,19 @@ class SlaveRecParser extends Module{
)), STATE_HEADER )), STATE_HEADER
), ),
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, ( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER), ), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U), Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA )
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
), STATE_PAYLOAD_DATA )
), STATE_PAYLOAD_DATA), ), STATE_PAYLOAD_DATA),
( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === ( (2 - 1).U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
),STATE_SUBMSG_TAIL )
), STATE_SUBMSG_TAIL),
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
), ),

87
src/main/scala/backBoard/shin/SlaveSendGen.scala
View File

@@ -15,7 +15,8 @@ class SlaveSendGenIO extends Bundle{
val frameReq = Flipped(Decoupled( new FrameHeader )) val frameReq = Flipped(Decoupled( new FrameHeader ))
val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo )) val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo ))
val subMsgTailReq = Flipped(Decoupled( new SubMsgTail ))
val send = Decoupled(new AXIS_Bundle(8)) val send = Decoupled(new AXIS_Bundle(8))
@@ -39,8 +40,8 @@ class SlaveSendGen extends Module{
val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_SUBMSG_HEADER = 2.U val STATE_SUBMSG_HEADER = 2.U
val STATE_SUBMSG_DATA = 3.U val STATE_SUBMSG_DATA = 3.U
val STATE_CRC = 4.U //CRC校验 val STATE_SUBMSG_TAIL = 4.U
//val STATE_ERROR = 5.U val STATE_CRC = 5.U //CRC校验
val STATE_WAIT = 6.U val STATE_WAIT = 6.U
@@ -64,22 +65,22 @@ class SlaveSendGen extends Module{
val frameInfo = Reg(new FrameHeader) val frameInfo = Reg(new FrameHeader)
val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } val subMsgHeadInfo = Reg(new SubMsgTxInfo)
val subMsgTailInfo = Reg(new SubMsgTail)
val isPingFill = RegInit(false.B)
val isPingEmit = RegInit(false.B)
when( io.frameReq.fire ){ when( io.frameReq.fire ){
frameInfo := io.frameReq.bits frameInfo := io.frameReq.bits
} }
when( io.subMsgReq.fire ){ when( io.subMsgHeadReq.fire ){
when( isPingFill ){ subMsgHeadInfo := io.subMsgHeadReq.bits
subMsgInfo(0) := io.subMsgReq.bits }
} .otherwise{
subMsgInfo(1) := io.subMsgReq.bits when( io.subMsgTailReq.fire ){
} subMsgTailInfo := io.subMsgTailReq.bits
} }
@@ -90,7 +91,7 @@ class SlaveSendGen extends Module{
when( io.send.fire ){ when( io.send.fire ){
when( stateCurr === STATE_FRAME_HEADER ){ when( stateCurr === STATE_FRAME_HEADER ){
frameLenCnt := 0.U frameLenCnt := 0.U
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){ } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){
frameLenCnt := frameLenCnt + 1.U frameLenCnt := frameLenCnt + 1.U
} }
} }
@@ -104,36 +105,38 @@ class SlaveSendGen extends Module{
val subMsgInfoSel = Mux( isPingEmit, subMsgInfo(0), subMsgInfo(1) )
io.frameReq.ready := true.B io.frameReq.ready := true.B
io.subMsgReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL
stateNext := Mux1H(Seq( stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
(stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux(
frameInfo.frameStyle === FRAME_STYLE_COMMON, frameInfo.frameStyle === FRAME_STYLE_COMMON,
Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
STATE_CRC ), STATE_CRC ),
STATE_FRAME_HEADER), STATE_FRAME_HEADER ), STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
(stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
(stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire,
Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文
STATE_SUBMSG_DATA ),
(stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire,
Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾
Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
STATE_SUBMSG_DATA STATE_SUBMSG_TAIL
), STATE_SUBMSG_DATA ), ), STATE_SUBMSG_TAIL ),
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
)) ))
io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U) io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U)
io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U) io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U)
assert( ~(io.data(0).ready & ~io.data(0).valid) ) assert( ~(io.data(0).ready & ~io.data(0).valid) )
assert( ~(io.data(1).ready & ~io.data(1).valid) ) assert( ~(io.data(1).ready & ~io.data(1).valid) )
@@ -143,7 +146,8 @@ class SlaveSendGen extends Module{
io.send.valid := io.send.valid :=
(stateCurr === STATE_FRAME_HEADER) | (stateCurr === STATE_FRAME_HEADER) |
(stateCurr === STATE_SUBMSG_HEADER) | (stateCurr === STATE_SUBMSG_HEADER) |
(stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgInfoSel.source === 0.U) | (io.data(1).valid & subMsgInfoSel.source === 1.U) )) | (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) |
(stateCurr === STATE_SUBMSG_TAIL) |
(stateCurr === STATE_CRC) (stateCurr === STATE_CRC)
@@ -155,25 +159,29 @@ class SlaveSendGen extends Module{
)) ))
val tdata_submsg_header = Mux1H(Seq( val tdata_submsg_header = Mux1H(Seq(
(lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6), (lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6),
(lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style), (lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style),
(lengthCnt === 2.U) -> subMsgInfoSel.address(15,8), (lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8),
(lengthCnt === 3.U) -> subMsgInfoSel.address(7,0), (lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0),
(lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)), (lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)),
(lengthCnt === 5.U) -> subMsgInfoSel.length(7,0), (lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0),
(lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8),
(lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0),
)) ))
val tdata_submsg_data = Mux1H(Seq( val tdata_submsg_data = Mux1H(Seq(
(subMsgInfoSel.source === 0.U) -> io.data(0).bits, (subMsgHeadInfo.source === 0.U) -> io.data(0).bits,
(subMsgInfoSel.source === 1.U) -> io.data(1).bits, (subMsgHeadInfo.source === 1.U) -> io.data(1).bits,
))
val tdata_submsg_tail = Mux1H(Seq(
(lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8),
(lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0),
)) ))
crc.io.dataIn := Mux1H(Seq( crc.io.dataIn := Mux1H(Seq(
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
)) ))
@@ -188,6 +196,7 @@ class SlaveSendGen extends Module{
(stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header,
(stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
(stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data,
(stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail,
(stateCurr === STATE_CRC) -> tdata_crc, (stateCurr === STATE_CRC) -> tdata_crc,
)) ))