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同步校准+spi lvds写入确认

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This commit is contained in:
RuigeLee
2025-09-02 18:50:39 +08:00
parent 826b35b830
commit 864a7d3d23
1 changed files with 41 additions and 23 deletions
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64
src/main/scala/backBoard/shin/Interface.scala
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@@ -785,7 +785,8 @@ trait InterfaceSync{ this: InterfaceBase =>
cReg.syncWidth(i) := syncWidth(i)
}
val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint
val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint
val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W))
val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid
val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0
@@ -807,21 +808,22 @@ trait InterfaceSync{ this: InterfaceBase =>
}
when( addrw === "h130".U ){
syncPoint := Cat( syncPoint(63,8), dataw )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), dataw )
} .elsewhen( addrw === "h131".U ){
syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), dataw, syncPoint_WRCopy(7,0) )
} .elsewhen( addrw === "h132".U ){
syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), dataw, syncPoint_WRCopy(15,0) )
} .elsewhen( addrw === "h133".U ){
syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), dataw, syncPoint_WRCopy(23,0) )
} .elsewhen( addrw === "h134".U ){
syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), dataw, syncPoint_WRCopy(31,0) )
} .elsewhen( addrw === "h135".U ){
syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), dataw, syncPoint_WRCopy(39,0) )
} .elsewhen( addrw === "h136".U ){
syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), dataw, syncPoint_WRCopy(47,0) )
} .elsewhen( addrw === "h137".U ){
syncPoint := Cat( dataw, syncPoint(55,0) )
syncPoint_WRCopy := Cat( dataw, syncPoint_WRCopy(55,0) )
syncPoint := Cat( dataw, syncPoint_WRCopy(55,0) )
}
.elsewhen( addrw === "h138".U ){
@@ -867,7 +869,6 @@ trait InterfaceSync{ this: InterfaceBase =>
}
when( io.lvds.isEnW ){
when( io.lvds.addrw === "h120".U ){
@@ -883,21 +884,22 @@ trait InterfaceSync{ this: InterfaceBase =>
}
.elsewhen( io.lvds.addrw === "h130".U ){
syncPoint := Cat( syncPoint(63,8), io.lvds.dataw )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === "h131".U ){
syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), io.lvds.dataw, syncPoint_WRCopy(7,0) )
} .elsewhen( io.lvds.addrw === "h132".U ){
syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), io.lvds.dataw, syncPoint_WRCopy(15,0) )
} .elsewhen( io.lvds.addrw === "h133".U ){
syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), io.lvds.dataw, syncPoint_WRCopy(23,0) )
} .elsewhen( io.lvds.addrw === "h134".U ){
syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), io.lvds.dataw, syncPoint_WRCopy(31,0) )
} .elsewhen( io.lvds.addrw === "h135".U ){
syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), io.lvds.dataw, syncPoint_WRCopy(39,0) )
} .elsewhen( io.lvds.addrw === "h136".U ){
syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) )
syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), io.lvds.dataw, syncPoint_WRCopy(47,0) )
} .elsewhen( io.lvds.addrw === "h137".U ){
syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) )
syncPoint_WRCopy := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
syncPoint := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) )
}
.elsewhen( io.lvds.addrw === "h138".U ){
@@ -923,7 +925,7 @@ trait InterfaceSync{ this: InterfaceBase =>
}
}
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U(64.W) )
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 1.U(64.W) )
cReg.mstDeltaTime := io.mstDeltaTime
@@ -938,24 +940,40 @@ trait InterfaceSync{ this: InterfaceBase =>
val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
val recoTimeStamp_Copy = RegInit(1.U(64.W))
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when(
cReg.syncPoint === recoTimeStamp_Copy ||
(io.lvds.addrw === "h120".U & io.lvds.isEnW) || //写syncCfg
(io.lvds.addrw === "h137".U & io.lvds.isEnW) || //写syncPoint
(io.lvds.addrw === "h13B".U & io.lvds.isEnW) || //写syncPeroid
(addrw === "h120".U & isEnW) || //写syncCfg
(addrw === "h137".U & isEnW) || //写syncPoint
(addrw === "h13B".U & isEnW) //写syncPeroid
){
recoTimeStamp_Copy := cReg.timeStamp + sReg.deltaFinal
} .otherwise{
recoTimeStamp_Copy := recoTimeStamp_Copy + 1.U
}
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
syncSign(0) := true.B
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
syncSign(0) := false.B
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
syncSign(0) := false.B
}
when( cReg.syncPoint <= cReg.recoTimeStamp ){
when( cReg.syncPoint <= recoTimeStamp_Copy ){
syncPoint := syncPoint + cReg.syncPeroid
}
for( i <- 1 until 4 ) {
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点
syncOffsetCnt(i) := 0.U
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U