From 862028dac76cb7aa279762feeb761c0104bb1256 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 28 Jun 2024 14:44:04 +0800 Subject: [PATCH] =?UTF-8?q?dout16=E5=A2=9E=E5=8A=A0=E4=B8=80=E4=B8=AAerr?= =?UTF-8?q?=E7=81=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/Dout16.scala | 3 +++ src/main/verilog/do16_top.v | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala index bd5aff9..351e75e 100644 --- a/src/main/scala/backBoard/Dout16.scala +++ b/src/main/scala/backBoard/Dout16.scala @@ -25,8 +25,11 @@ with BackBoardSlvOut16{ val out = IO(Output(UInt(16.W))) val flt = IO(Input(Vec(2, Bool()))) val v24Det = IO(Input(Bool())) + val LED_ERR = IO(Output(Bool())) val outReg = RegInit(0.U(16.W)) + LED_ERR := v24Det + when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ outReg := Cat(downRegTemp(3), downRegTemp(2)) } diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v index aa06293..80745bd 100644 --- a/src/main/verilog/do16_top.v +++ b/src/main/verilog/do16_top.v @@ -20,6 +20,7 @@ module do16_top( input DCIn, output LED_PR, + output LED_ERR, output [15:0] out, input flt_0, input flt_1, @@ -295,6 +296,7 @@ DOut16 i_dout16( // .param_batchID(`BATCHID), .param_serial(`SERIAL), .LED_PR(LED_PR), + .LED_ERR(LED_ERR), .out(out), .flt_0(flt_0), .flt_1(flt_1),