diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index d4d9546..8360edb 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -58,7 +58,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
   withClockAndReset( io.ides_pclk.asClock, io.reset ){
     val statusReg = RegInit(0.U(8.W)); status := statusReg
-    val slvNumReg = RegInit(0.U(5.W)); slvNum := slvNumReg
+    val slvNumReg = RegInit(31.U(5.W)); slvNum := slvNumReg
 
     val fsmcAddrSync   = ShiftRegister( io.FSMC.addr,   2, 0.U, true.B )
     val fsmcdataInSync = ShiftRegister( io.FSMC.dataIn, 2, 0.U, true.B )
@@ -117,103 +117,99 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
   lvdsMst.io.tx_start := false.B
 
 
+  val trigger_wire = Wire(Bool())
+  val stateCur_wire = Wire( UInt(4.W) )
 
-  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+  withClockAndReset( io.oser_pclk.asClock, io.reset ){
 
-    val stateCur = RegInit(5.U(3.W))
-    val ( cnt, trigger ) = Counter(Range( 0,1023))
+    val stateCur = RegInit(3.U(4.W))
+    stateCur_wire := stateCur
 
-    val addrr = RegInit(0.U)
-    val addrw = RegInit(0.U)
+    // val outOfInit = RegInit(false.B)
 
-    when( trigger ){
+    // val ( _, init ) = Counter(Range( 0,4096))
+    // when( init ) { outOfInit := true.B }
+
+    val ( _, trigger ) = Counter(Range( 0,2000) )
+    trigger_wire := trigger
+
+    val isSync = RegInit(false.B)
+
+
+    val frame_info_update_en = RegInit(false.B)
+
+    val slave_type_num       = RegInit(0.U(8.W))
+    val slave_data_length    = RegInit(0.U(8.W))
+    val tx_start             = RegInit(false.B)
+
+    lvdsMst.io.frame_info_update_en := frame_info_update_en
+    lvdsMst.io.slave_type_num       := slave_type_num
+    lvdsMst.io.slave_data_length    := slave_data_length
+    lvdsMst.io.tx_start := tx_start
+
+
+
+    when( trigger ){  //reset
       stateCur := 0.U
 
-      addrr := 0.U
-      addrw := 0.U
+      frame_info_update_en := false.B
+      slave_type_num       := 0.U
+      slave_data_length    := 0.U
 
-      lvdsMst.io.frame_info_update_en := true.B
-      lvdsMst.io.slave_type_num       := Cat( "b000".U(3.W), slvNum )
-      lvdsMst.io.slave_data_length    := (8/8*4*8-1).U
+      tx_start := false.B
+      
+      isSync := ~isSync
 
-      lvdsMst.io.tx_start := false.B
-    } .elsewhen( stateCur === 0.U ){
+    } .elsewhen( stateCur === 0.U  ){ //setting
       stateCur := 1.U
 
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
 
-      lvdsMst.io.tx_start := true.B
 
-    } .elsewhen( stateCur === 1.U ){
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
+      frame_info_update_en := true.B
+      slave_type_num       := Mux(isSync, Cat( "b000".U(3.W), slvNum ), Cat( "b10".U(2.W), 0.U(6.W) ) )
+      slave_data_length    := Mux(isSync, (8/8*4*8-1).U, 0.U )
 
-      lvdsMst.io.tx_start := false.B
+      tx_start := false.B
+    } .elsewhen( stateCur === 1.U ){ // tx start
+      stateCur := 2.U
+
+      frame_info_update_en := false.B
+      tx_start := true.B
+
+    } .elsewhen( stateCur === 2.U ){ //waiting  for busy drop
+
+      tx_start := false.B
 
       when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
-        stateCur := 2.U
+        stateCur := 3.U
       }
 
-    } .elsewhen( stateCur === 2.U ){
-      stateCur := 3.U
-
-      lvdsMst.io.frame_info_update_en := true.B
-      lvdsMst.io.slave_type_num       := Cat( "b10".U(2.W), 0.U(6.W) )
-      lvdsMst.io.slave_data_length    := 0.U
-      lvdsMst.io.tx_start := false.B
-      addrr := 0.U
-      addrw := 0.U
-
     } .elsewhen( stateCur === 3.U ){
-
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
-      lvdsMst.io.tx_start := true.B
-
-    } .elsewhen( stateCur === 4.U ){
-
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
-
-      lvdsMst.io.tx_start := false.B
-
-      when( lvdsMst.io.tx_data_ready ){
-        addrr := addrr + 1.U
-      }
-      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
-        stateCur := 5.U
-      }
-    } .elsewhen( stateCur === 5.U ){
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
-
-      lvdsMst.io.tx_start := false.B
-
+      
     } .otherwise{
 
-      lvdsMst.io.frame_info_update_en := false.B
-      lvdsMst.io.slave_type_num       := 0.U
-      lvdsMst.io.slave_data_length    := 0.U
-
-      lvdsMst.io.tx_start := false.B
-
       assert(false.B)
     }
+  }
 
-    when( lvdsMst.io.rx_data_valid ){
-      assert( (stateCur === 4.U) || (stateCur === 5.U) )
+  withClockAndReset( io.ides_pclk.asClock, io.reset ){
+    val addrr = RegInit(0.U)
+    val addrw = RegInit(0.U)
+
+    when( trigger_wire ){
+      addrw := 0.U
+    } .elsewhen( lvdsMst.io.rx_data_valid ){
+      assert( (stateCur_wire === 2.U) || (stateCur_wire === 3.U) )
       addrw := addrw + 1.U
     }
 
+    when( trigger_wire ){
+      addrr := 0.U
+    } .elsewhen( lvdsMst.io.tx_data_ready ){
+      addrr := addrr + 1.U
+    }
 
-
-    mirrorDown.io.enr := (stateCur === 3.U || stateCur === 4.U)
+    mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U)
     lvdsMst.io.tx_data_in := mirrorDown.io.datar
     mirrorDown.io.addrr := addrr
     
diff --git a/src/main/scala/backBoard/goWinBus.scala b/src/main/scala/backBoard/goWinBus.scala
index b071df8..f715f0d 100644
--- a/src/main/scala/backBoard/goWinBus.scala
+++ b/src/main/scala/backBoard/goWinBus.scala
@@ -42,7 +42,7 @@ class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
 
   val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
 
-  setInline("lvds_bus_master.v",
+  setInline("lvds_Bus_Master.v",
               """
   | module Lvds_Bus_Master(
   | input rst_n,
@@ -129,7 +129,7 @@ class Lvds_Bus_SlaveIO extends Bundle{
 class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
   val io: Lvds_Bus_SlaveIO = IO(new Lvds_Bus_SlaveIO)
 
-  setInline("lvds_bus_slave.v",
+  setInline("Lvds_Bus_Slave.v",
               """
   module Lvds_Bus_Slave(
   |  input rst_n,