集合master 和slave 测试恢复

src/main/scala/backBoard/shin/MasterParser.scala

@@ -3,18 +3,18 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-class MasterParserIO extends Module{
+class MasterParserIO extends Bundle{
   val downOut = Decoupled(new AXIS_Bundle(8))
   val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
 
-  val sram_r = Flipped(new ShareSRAMIO)
+  val sram_w = Flipped(new SRAM2kWRIO)
-  val sram_w = Flipped(new ShareSRAMIO)
+  val sram_r = Flipped(new SRAM2kRDIO)
 
-  val req = Valid(new Bundle{
+  val req = Flipped(Valid(new Bundle{
     val txAddr    = UInt(15.W)
     val rxAddr    = UInt(15.W)
     val length  = UInt(12.W)
-  })
+  }))
   val rsp = Valid(new Bundle{
     val isError = Bool()
     val length  = UInt(12.W)
@@ -32,29 +32,29 @@ class MasterParserIO extends Module{
 abstract class MasterParserBase extends Module{
   val io: MasterParserIO = IO(new MasterParserIO)
 
-  val sendCnt = Reg(UInt(11.W))
+  val txCnt = Reg(UInt(11.W))
-  val sendLen = Reg(UInt(11.W))
+  val txLen = Reg(UInt(11.W))
   val txAddr = Reg(UInt(15.W))
 
   val rxCnt = Reg(UInt(11.W))
   val rxAddr = Reg(UInt(15.W))
 
   val reqReady = RegInit(true.B)
-  val sendAddr = Reg(UInt(12.W))
 
-  io.req.ready := reqReady
+
+  // io.req.ready := reqReady
 
   when( io.req.fire ){
     reqReady := false.B
-  } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
+  } .elsewhen( io.downOut.fire & txCnt === txLen ){
     reqReady := true.B
   }
 
   when( io.req.fire ){
-    sendLen  := io.req.bits.length
+    txLen  := io.req.bits.length
-    sendCnt  := 0.U
+    txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
-    sendCnt := sendCnt + 1.U
+    txCnt := txCnt + 1.U
   }
 
   when( io.req.fire ){
@@ -69,21 +69,17 @@ abstract class MasterParserBase extends Module{
     rxAddr := rxAddr + 1.U
   }
 
-  when( reqReady ){
+
-    sendAddr := 0.U
-  } .elsewhen( io.downOut.fire ){
-    sendAddr := sendAddr + 1.U
-  }
 
   io.sram_r.enr := 
     io.req.fire | io.downOut.fire
 
-  io.sram_r.addr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
   io.downOut.bits.tdata := io.sram_r.datar
   io.downOut.bits.tuser := false.B 
-  io.downOut.bits.tlast := sendCnt === sendLen
+  io.downOut.bits.tlast := txCnt === txLen
 
 
 
@@ -99,7 +95,7 @@ abstract class MasterParserBase extends Module{
   io.upIn.ready := true.B
 
   io.sram_w.enw := io.upIn.fire
-  io.sram_w.addr := rxAddr
+  io.sram_w.addrw := rxAddr
   io.sram_w.dataw := io.upIn.bits.tdata
 
 

src/main/scala/backBoard/shin/ShareSRAM.scala

@@ -110,11 +110,11 @@ class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
 
   | module ShareSRAM2k(
   |   	input [7:0] dataw,
-  |   	input [10:0] addrw,
+  |   	input [14:0] addrw,
   |   	input enw,
   |   
   |   	output [7:0] datar,
-  |   	input [10:0] addrr,
+  |   	input [14:0] addrr,
   |   	input enr,
   |   
   |   	input clockr,

src/main/scala/backBoard/shin/ShinTop.scala

@@ -33,6 +33,19 @@ class ShinTopIO extends Bundle{
 
 
   val modeSel = Input(Bool())
+
+
+
+
+  val req = Flipped(Valid(new Bundle{
+    val txAddr    = UInt(15.W)
+    val rxAddr    = UInt(15.W)
+    val length  = UInt(12.W)
+  }))
+  val rsp = Valid(new Bundle{
+    val isError = Bool()
+    val length  = UInt(12.W)
+  })
 }
 
 
@@ -98,27 +111,7 @@ abstract class ShinTopBase extends Module{
 
 
 
-  when( io.modeSel === false.B ){
-    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
-    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
-    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
-    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
 
-    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
-    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
-    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
-    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
-
-    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
-    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
-    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
-    smUnit(6).io.enq := slaveParser.io.dSMenq(3)
-
-    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
-    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
-    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
-    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)    
-  }
 
 
 
@@ -153,11 +146,58 @@ abstract class ShinTopBase extends Module{
 
 
 
-  when(io.modeSel === false.B ){
+
-    slaveParser.io.downIn  <> io.downIn
+  //default
-    slaveParser.io.downOut <> io.downOut
+  {
-    slaveParser.io.upIn    <> io.upIn
+    smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
-    slaveParser.io.upOut   <> io.upOut    
+    smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
+    smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
+    smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
+
+    smUnit(1).io.sram_r.enr := false.B
+    smUnit(3).io.sram_r.enr := false.B
+    smUnit(5).io.sram_r.enr := false.B
+    smUnit(7).io.sram_r.enr := false.B
+    smUnit(1).io.sram_r.addrr := 0.U
+    smUnit(3).io.sram_r.addrr := 0.U
+    smUnit(5).io.sram_r.addrr := 0.U
+    smUnit(7).io.sram_r.addrr := 0.U
+
+    slaveParser.io.sram_r(0).datar := 0.U
+    slaveParser.io.sram_r(1).datar := 0.U
+    slaveParser.io.sram_r(2).datar := 0.U
+    slaveParser.io.sram_r(3).datar := 0.U
+    masterParser.io.sram_r.datar := 0.U
+
+    smUnit(0).io.enq := false.B
+    smUnit(2).io.enq := false.B
+    smUnit(4).io.enq := false.B
+    smUnit(6).io.enq := false.B
+
+    smUnit(1).io.deq := false.B
+    smUnit(3).io.deq := false.B
+    smUnit(5).io.deq := false.B
+    smUnit(7).io.deq := false.B
+
+
+    io.downIn.ready := false.B
+    slaveParser.io.downIn.valid := false.B
+    slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
+
+    slaveParser.io.downOut.ready := false.B
+    masterParser.io.downOut.ready := false.B
+    io.downOut.valid := false.B
+    io.downOut.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
+
+    io.upIn.ready := false.B
+    slaveParser.io.upIn.valid := false.B
+    slaveParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
+    masterParser.io.upIn.valid := false.B
+    masterParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
+
+    slaveParser.io.upOut.ready := false.B
+    io.upOut.valid := false.B
+    io.upOut.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
   }
 
 
@@ -172,34 +212,24 @@ abstract class ShinTopBase extends Module{
 
 
 trait ShinTopMaster{ this: ShinTopBase =>
-    val downOut = Decoupled(new AXIS_Bundle(8))
-    val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
 
+  when(io.modeSel === true.B ){
+    slaveParser.io.downOut <> io.downOut
+    slaveParser.io.upIn    <> io.upIn 
+  }
 
   when( io.modeSel === true.B ){
-    smUnit(0).io.sram_w := masterParser.io.sram_w(0)
+    smUnit(0).io.sram_w := masterParser.io.sram_w
-    smUnit(1).io.sram_r <> masterParser.io.sram_r(0)
+    smUnit(1).io.sram_r <> masterParser.io.sram_r
 
 
-    smUnit(0).io.enq := slaveParser.io.rxEnq
+    smUnit(0).io.enq := masterParser.io.rxEnq
-    smUnit(1).io.deq := slaveParser.io.txDeq
+    smUnit(1).io.deq := masterParser.io.txDeq
 
   }
-    val sram_r = Flipped(new ShareSRAMIO)
-    val sram_w = Flipped(new ShareSRAMIO)
 
-    val req = Valid(new Bundle{
+  masterParser.io.req := io.req
-      val txAddr    = UInt(15.W)
+  io.rsp := masterParser.io.rsp
-      val rxAddr    = UInt(15.W)
-      val length  = UInt(12.W)
-    })
-    val rsp = Valid(new Bundle{
-      val isError = Bool()
-      val length  = UInt(12.W)
-    })
-
-    val txDeq = Output( Bool())
-    val rx Enq  = Output( Bool())
 
   masterParser.io.trigAddr(0) := "hff".U
   masterParser.io.trigAddr(1) := "hff".U
@@ -257,7 +287,12 @@ trait ShinTopSlave{ this: ShinTopBase =>
   }
 
 
-
+  when(io.modeSel === false.B ){
+    slaveParser.io.downIn  <> io.downIn
+    slaveParser.io.downOut <> io.downOut
+    slaveParser.io.upIn    <> io.upIn
+    slaveParser.io.upOut   <> io.upOut    
+  }
 
 
 }

tb/shinTest/ShinTopTb.v

@@ -41,6 +41,10 @@ reg [63:0] timeStamp = 0;
 
 
 
+
+
+
+
 ShinTop s_ShinTop(
   .clock(clock),
   .reset(reset),
@@ -100,8 +104,17 @@ ShinTop s_ShinTop(
   .io_sram_r_2_enr(1'b0),
   .io_sram_r_3_addrr(11'd0),
   .io_sram_r_3_datar(),
-  .io_sram_r_3_enr(1'b0)
+  .io_sram_r_3_enr(1'b0),
 
+  .io_modeSel(1'b0),
+
+  .io_req_valid(1'b0),
+  .io_req_bits_txAddr(15'h0),
+  .io_req_bits_rxAddr(15'h0),
+  .io_req_bits_length(12'd0),
+  .io_rsp_valid(),
+  .io_rsp_bits_isError(),
+  .io_rsp_bits_length()
 );