集合master 和slave 测试恢复

src/main/scala/backBoard/shin/MasterParser.scala

@@ -3,18 +3,18 @@ package BACK
 import chisel3._
 import chisel3.util._
 
-class MasterParserIO extends Module{
+class MasterParserIO extends Bundle{
   val downOut = Decoupled(new AXIS_Bundle(8))
   val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
 
-  val sram_r = Flipped(new ShareSRAMIO)
-  val sram_w = Flipped(new ShareSRAMIO)
+  val sram_w = Flipped(new SRAM2kWRIO)
+  val sram_r = Flipped(new SRAM2kRDIO)
 
-  val req = Valid(new Bundle{
+  val req = Flipped(Valid(new Bundle{
     val txAddr    = UInt(15.W)
     val rxAddr    = UInt(15.W)
     val length  = UInt(12.W)
-  })
+  }))
   val rsp = Valid(new Bundle{
     val isError = Bool()
     val length  = UInt(12.W)
@@ -32,29 +32,29 @@ class MasterParserIO extends Module{
 abstract class MasterParserBase extends Module{
   val io: MasterParserIO = IO(new MasterParserIO)
 
-  val sendCnt = Reg(UInt(11.W))
-  val sendLen = Reg(UInt(11.W))
+  val txCnt = Reg(UInt(11.W))
+  val txLen = Reg(UInt(11.W))
   val txAddr = Reg(UInt(15.W))
 
   val rxCnt = Reg(UInt(11.W))
   val rxAddr = Reg(UInt(15.W))
 
   val reqReady = RegInit(true.B)
-  val sendAddr = Reg(UInt(12.W))
 
-  io.req.ready := reqReady
+
+  // io.req.ready := reqReady
 
   when( io.req.fire ){
     reqReady := false.B
-  } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
+  } .elsewhen( io.downOut.fire & txCnt === txLen ){
     reqReady := true.B
   }
 
   when( io.req.fire ){
-    sendLen  := io.req.bits.length
-    sendCnt  := 0.U
+    txLen  := io.req.bits.length
+    txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
-    sendCnt := sendCnt + 1.U
+    txCnt := txCnt + 1.U
   }
 
   when( io.req.fire ){
@@ -69,21 +69,17 @@ abstract class MasterParserBase extends Module{
     rxAddr := rxAddr + 1.U
   }
 
-  when( reqReady ){
-    sendAddr := 0.U
-  } .elsewhen( io.downOut.fire ){
-    sendAddr := sendAddr + 1.U
-  }
+
 
   io.sram_r.enr := 
     io.req.fire | io.downOut.fire
 
-  io.sram_r.addr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
   io.downOut.bits.tdata := io.sram_r.datar
   io.downOut.bits.tuser := false.B 
-  io.downOut.bits.tlast := sendCnt === sendLen
+  io.downOut.bits.tlast := txCnt === txLen
 
 
 
@@ -99,7 +95,7 @@ abstract class MasterParserBase extends Module{
   io.upIn.ready := true.B
 
   io.sram_w.enw := io.upIn.fire
-  io.sram_w.addr := rxAddr
+  io.sram_w.addrw := rxAddr
   io.sram_w.dataw := io.upIn.bits.tdata