diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala
index 5bc6a8b..13ddbef 100644
--- a/src/main/scala/backBoard/shin/ShinMst.scala
+++ b/src/main/scala/backBoard/shin/ShinMst.scala
@@ -6,8 +6,8 @@ import chisel3.util._
 
 
 class Header_Info_Bundle extends Bundle{
-  val length   = UInt(8.W) // nlength * 16bits
-  val operator = UInt(8.W)
+  val length   = UInt(12.W) // nlength * 8bits
+  val operator = UInt(4.W)
   val param    = Vec(3, UInt(16.W))
 
   def init = operator === 0.U
@@ -82,6 +82,7 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
 
   val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
   val sendHeader = Reg( new Header_Info_Bundle )
+  val sendHead = sendHeader.asUInt
 
 
 
@@ -128,7 +129,7 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
   sendStateNext := Mux1H(Seq(
     (sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
     (sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === ((headByte)-1).U, 2.U, 1.U ),
-    (sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (sendHeader.length << 1) - 1.U,    3.U, 2.U ),
+    (sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (sendHeader.length ) - 1.U,    3.U, 2.U ),
     (sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
   ))
 
@@ -143,10 +144,10 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
   cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
   cdrOut.io.axis.bits.tdata := 
     Mux1H(Seq(
-      ( sendStateCurr === 1.U ) -> (sendHeader.asUInt >> (sendCntCurr << 3)),
+      ( sendStateCurr === 1.U ) -> (sendHead << (sendCntCurr << 3)).apply(63,56),
       ( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ),
     ))
-  cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length << 1) - 1.U
+  cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length - 1.U )
   cdrOut.io.axis.bits.tuser := false.B
 
   mirrorDown.io.enwB := false.B
@@ -178,7 +179,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
     (recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
     (recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
     (recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth/8-1)*2).U, 3.U, 2.U ), //Header
-    (recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength << 1), 4.U, 3.U ), //payload
+    (recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength), 4.U, 3.U ), //payload
     (recvStateCurr === 4.U) -> 0.U, //de-Arm
   ))
 
@@ -215,7 +216,7 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
     recvRamAddr := recvRamAddr + 1.U
   }
 
-  mirrorReg.io.addrB  := recvRamAddr
+
   mirrorReg.io.datawB := Mux1H(Seq(
     (recvStateCurr === 3.U & recvRamAddr === 0.U) -> (recvHeader >> 16*3),
     (recvStateCurr === 3.U & recvRamAddr === 1.U) -> (recvHeader >> 16*2),
@@ -223,8 +224,11 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
     (recvStateCurr === 3.U & recvRamAddr === 3.U) -> (recvHeader >> 16*0),
   ))
   
-  mirrorReg.io.enwB   := recvStateCurr === 3.U & recvRamAddr =/= 4.U
-
+  
+  when( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
+    mirrorReg.io.addrB  := recvRamAddr
+    mirrorReg.io.enwB   := true.B
+  }
 
 
   val isTimeout: Bool
diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala
index 108f260..1e44a37 100644
--- a/src/main/scala/backBoard/shin/ShinSlv.scala
+++ b/src/main/scala/backBoard/shin/ShinSlv.scala
@@ -161,7 +161,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
   } .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( isLastDevice & downOldHead.length =/= downLocalDataByte ){
+  } .elsewhen( isDownNewHeadCreated & isLastDevice & downOldHead.length =/= downLocalDataByte ){
     printf("Warning, Wrong Package Received in DownStream, SoftWare Check!\n")
   }
 
@@ -207,7 +207,7 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
     downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData
 
   downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
-    ( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).head(8),
+    ( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).apply(63,56),
     ( downSendStateCurr === DownSendStateFData ) -> downStreamFifo.io.deq.bits.tdata,
   ))
 
@@ -391,7 +391,7 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
     upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
 
   upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
-    ( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).head(8),
+    ( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).apply(63,56),
     ( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
     ( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata,
   ))
diff --git a/tb/ShinBack_tb.v b/tb/ShinBack_tb.v
index 525b9f8..5ed33ae 100644
--- a/tb/ShinBack_tb.v
+++ b/tb/ShinBack_tb.v
@@ -10,7 +10,7 @@ module ShinBack_tb();
 
     reg clock = 0;
     reg overClk = 0;
-    reg reset = 0;
+    reg reset = 1;
 
     reg  [15:0] io_FSMC_ADIn;
     wire [15:0] io_FSMC_ADOut;
@@ -129,25 +129,25 @@ initial begin
     io_FSMC_advn = 1;
     io_testIO = 0;
 
-    #1000
+    #5005
 
 
 // @0 <- 512 length | operator
-    #100
-    io_FSMC_ADIn = 16'd0;
+    #500
+    io_FSMC_ADIn = 16'd0 | (1 << 11);
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 1;
     io_FSMC_advn = 0;
 
-    #100
-    io_FSMC_ADIn = 16'd512 << 8 | 16'd0;
+    #500
+    io_FSMC_ADIn = (16'd512 << 4) | 16'd0;
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 0;
     io_FSMC_advn = 1;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 1;
     io_FSMC_rdn = 1;
@@ -155,21 +155,21 @@ initial begin
     io_FSMC_advn = 1;
 
 // @1 <- 0 param0
-    #100
-    io_FSMC_ADIn = 16'd1;
+    #500
+    io_FSMC_ADIn = 16'd1 | (1 << 11);
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 1;
     io_FSMC_advn = 0;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 0;
     io_FSMC_advn = 1;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 1;
     io_FSMC_rdn = 1;
@@ -177,21 +177,21 @@ initial begin
     io_FSMC_advn = 1;
 
 // @2 <- 0 param1
-    #100
-    io_FSMC_ADIn = 16'd2;
+    #500
+    io_FSMC_ADIn = 16'd2 | (1 << 11);
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 1;
     io_FSMC_advn = 0;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 0;
     io_FSMC_advn = 1;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 1;
     io_FSMC_rdn = 1;
@@ -199,21 +199,21 @@ initial begin
     io_FSMC_advn = 1;
 
 // @3 <- 0 param2
-    #100
-    io_FSMC_ADIn = 16'd3;
+    #500
+    io_FSMC_ADIn = 16'd3 | (1 << 11);
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 1;
     io_FSMC_advn = 0;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 0;
     io_FSMC_rdn = 1;
     io_FSMC_wrn = 0;
     io_FSMC_advn = 1;
 
-    #100
+    #500
     io_FSMC_ADIn = 16'd0;
     io_FSMC_csn = 1;
     io_FSMC_rdn = 1;
@@ -221,9 +221,9 @@ initial begin
     io_FSMC_advn = 1;
 
 
-    #200
+    #800
     io_testIO = 1;
-    #80
+    #160
     io_testIO = 0;
 end