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采样头对齐问题，对齐哪个55和D5

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RuigeLee
2024-09-23 17:23:34 +08:00
parent 6750593b48
commit 833ad07525
1 changed files with 6 additions and 11 deletions
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17
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -98,7 +98,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext := stateNext :=
Mux1H(Seq( Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( /*(byteCnt === 7.U) &*/ (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE (stateCurr === STATE_IDLE) -> ( Mux( isArbLock & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -106,23 +106,18 @@ trait CDRInAxis{ this: CDRInBase =>
val isArbLock: Bool
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
when( byteCnt === 0.U & shiftData === ETH_PRE & stateCurr === STATE_IDLE ){ //first align
bitCnt := 0.U bitCnt := 0.U
} .otherwise{ } .otherwise{
bitCnt := bitCnt + 1.U bitCnt := bitCnt + 1.U
} }
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
byteCnt := 0.U
when( byteCnt === 0.U & shiftData === ETH_PRE & stateCurr === STATE_IDLE ){ //first align
byteCnt := 1.U
} .elsewhen( bitCnt === 7.U ){ } .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_IDLE ){ when( stateCurr === STATE_HEADER ){
byteCnt := Mux( /*byteCnt =/= 7.U &*/ shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass
/*assert( byteCnt <= 7.U )*/
} .elsewhen( stateCurr === STATE_HEADER ){
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U ) assert( byteCnt <= (HeaderByte-1).U )
} .elsewhen( stateCurr === STATE_PAYLOAD ){ } .elsewhen( stateCurr === STATE_PAYLOAD ){