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异步fifo

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RuigeLee
2023-10-10 16:48:32 +08:00
parent 201ab2579b
commit 82a6805e05
2 changed files with 82 additions and 4 deletions
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12
src/main/scala/mac/MacTilelink.scala
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@@ -72,13 +72,17 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val BlockingTxStatusWrite = Output(Bool())
val TxStartFrm_wb = Output(Bool())
val ReadTxDataFromFifo_sync = Input(Bool())
val TxStartFrm_syncb = Input(Bool())
val TxUnderRun_wb = Output(Bool())
val ReadTxDataFromFifo_sync = Input(Bool())
val TxData_wb = Output(UInt(32.W))
val TxValidBytesLatched = Output(UInt(2.W))
val TxStartFrm_wb = Output(Bool())
val TxStartFrm_syncb = Input(Bool())
val TxUnderRun_wb = Output(Bool())
val TxEndFrm_wb = Output(Bool())
val TxRetrySync = Input(Bool())