修复主站CRC校验逻辑（欠一拍）；增加22号寄存器，提示主站接收CRC错误

src/main/scala/backBoard/shin/Interface.scala

@@ -114,6 +114,7 @@ class MasterRegisterBundle extends Bundle{
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
 
+  val isRecCRCErr  = UInt(4.W)
   val rplTimeStampTx = UInt(16.W)
 }
 
@@ -264,6 +265,7 @@ abstract class InterfaceBase extends Module{
 
       Seq(
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
+        (addr === "h22".U & isMstMode) -> mReg.isRecCRCErr,
                 //(addr === "h21".U & isMstMode) -> mReg.txLength,
 
         (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
@@ -635,6 +637,16 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
   // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) )
 
+  val isMstRecCRCErr = RegInit(0.U(4.W))
+  mReg.isRecCRCErr := isMstRecCRCErr
+  when( isEnW & addrw === "h22".U(16.W) ){
+    isMstRecCRCErr := 0.U
+  } .elsewhen( io.upRecStat.isCRCError & isMstMode ){
+    isMstRecCRCErr := isMstRecCRCErr | (1.U << mReg.rxSM)
+  }
+
+
+
   ( 0 until 128 ).map{ i =>
     cReg.custom(i) := RegEnable( dataw, 0.U(8.W), isEnW & (addrw === ("h180".U(16.W) + i.U)) )
   }