无法初始化sram

Makefile

@@ -38,6 +38,7 @@ VSimTop:
 	-y ${PWD}/tb/verilator/ \
 	--top-module SimTop \
 	--trace-fst \
+	--no-timing \
 	--cc ./tb/verilator/SimTop.v  \
 	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
 	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
@@ -52,6 +53,7 @@ VSimTop:
 	-j 30
 
 
+
 test:
 	./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest
 
@@ -69,6 +71,7 @@ sw:
 
 	riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
 	-I ./tb/sw/ -I ./tb/sw/src \
+	-I ./tb/sw/tl2cdr \
 	-c ./tb/sw/src/mstMain.c \
 	-o ./tb/sw/build/mstMain.o
 
@@ -88,12 +91,13 @@ sw:
 	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
 
 	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.verilog
-	sed -i 's/@800/@000/g' ./tb/sw/build/mstTest.verilog
+	sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
 
 
 
 	riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
 	-I ./tb/sw/ -I ./tb/sw/src \
+	-I ./tb/sw/tl2cdr \
 	-c ./tb/sw/src/slvMain.c \
 	-o ./tb/sw/build/slvMain.o
 
@@ -118,7 +122,7 @@ sw:
 	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
 
 	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.verilog
-	sed -i 's/@800/@000/g' ./tb/sw/build/slvTest.verilog
+	sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
 
 	python3 ./tb/sw/bin_to_hex.py
 	python3 ./tb/sw/bin_to_coe.py

tb/sw/src/MstMain.c

@@ -5,8 +5,29 @@
 // #include "timer.h"
 #include "tl2cdr.h"
 
+volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
+volatile uint32_t *plic_enable_0_31  = (uint32_t*)( 0xc000000U + 0X002000 );
+volatile uint32_t *plic_claim        = (uint32_t*)( 0xc000000U + 0X200004 );
 
 
+uint32_t flag_intTxEnd = 0;
+uint32_t flag_intRxError = 0;
+uint32_t flag_intRxStart = 0;
+uint32_t flag_intRxEnd = 0;
+
+
+void trap_entry(){
+	if( *plic_claim == 3 ){
+		flag_intTxEnd = 1;
+	} else if( *plic_claim == 4 ){
+		flag_intRxError = 1;
+	} else if( *plic_claim == 5 ){
+		flag_intRxStart = 1;
+	} else if( *plic_claim == 6 ){
+		flag_intRxEnd = 1;
+	}
+	return;
+}
 
 
 
@@ -40,9 +61,12 @@ void main()
 
 	uint32_t led = 0;
 
+	*plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6;
+
 
 		*cdr_softReset = 1; //复位脉冲
 		*cdr_direct = 0;
+
 		register uint32_t flag;
 
 		asm volatile ( //timer 2s
@@ -75,26 +99,34 @@ void main()
 		}
 
 		//等待发送完成标志
-		asm volatile (
+								// asm volatile (
-			"1:\n"
+								// 	"1:\n"
-			"andi %0, sp, 0x01\n"
+								// 	"andi %0, sp, 0x01\n"
-			"beqz %0, 1b\n"
+								// 	"beqz %0, 1b\n"
-			"andi sp, sp, 0xFE\n"
+								// 	"andi sp, sp, 0xFE\n"
-			:"+r"(flag)
+								// 	:"+r"(flag)
-		);
+								// );
+
+		while( !flag_intTxEnd );
+		flag_intTxEnd = 0;
+
+
+
+
 
 		*cdr_softReset = 1; //复位脉冲
 		*cdr_direct = 1;    //方向切换上行
 
-
 		//接收第一个包
-		asm volatile (
+									// asm volatile (
-			"1:\n"
+									// 	"1:\n"
-			"andi %0, sp, 0x04\n"
+									// 	"andi %0, sp, 0x04\n"
-			"beqz %0, 1b\n"
+									// 	"beqz %0, 1b\n"
-			"andi sp, sp, 0xFB\n"
+									// 	"andi sp, sp, 0xFB\n"
-			:"+r"(flag)
+									// 	:"+r"(flag)
-		);
+									// );
+		while(!flag_intRxStart);
+		flag_intRxStart = 0;
 				
 		readDat = *cdr_rxFifo;	
 
@@ -111,38 +143,51 @@ void main()
 									// 	"bnez %0, 1b\n" //error //速度不够，不校验
 									// :"+r"(flag),
 									// );
+		if( flag_intRxError ){
+			while(1);
+		}
 
 		uint32_t temp = *cdr_rxFifo;
 
 		//上行转发负载
 		for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
-			register uint32_t upData;
+
-			asm volatile (
+			if( flag_intRxError ){
-				"andi %0, sp, 0x80\n"
+				while(1);
-				"1:\n"
+			}
-				"bnez %0, 1b\n" //error 速度不够，不再检查接收
+												// register uint32_t upData;
-				"lw %1, 0x01c(x0)\n"
+												// asm volatile (
-				:"+r"(flag), "+r"(upData)
+												// 	"andi %0, sp, 0x80\n"
-			);
+												// 	"1:\n"
+												// 	"bnez %0, 1b\n" //error 速度不够，不再检查接收
+												// 	"lw %1, 0x01c(x0)\n"
+												// 	:"+r"(flag), "+r"(upData)
+												// );
 		}
 
 		//CRC
-		asm volatile (
+		if( flag_intRxError ){
-			"andi %0, sp, 0x08\n"
+			while(1);
-			"1:\n"
+		}
-			"bnez %0, 1b\n" //error
+												// asm volatile (
-			:"+r"(flag)
+												// 	"andi %0, sp, 0x08\n"
-		);
+												// 	"1:\n"
+												// 	"bnez %0, 1b\n" //error
+												// 	:"+r"(flag)
+												// );
 		uint32_t crc = *cdr_rxFifo; //CRC
 
 		//等待接收完成标志
-		asm volatile (
+												// asm volatile (
-			"1:\n"
+												// 	"1:\n"
-			"andi %0, sp, 0x08\n"
+												// 	"andi %0, sp, 0x08\n"
-			"beqz %0, 1b\n"
+												// 	"beqz %0, 1b\n"
-			"andi sp, sp, 0xF7\n"
+												// 	"andi sp, sp, 0xF7\n"
-			:"+r"(flag)
+												// 	:"+r"(flag)
-		);
+												// );
+		
+		while(!flag_intRxEnd);
+		flag_intRxEnd = 0;
 
 		totNum = (upRecvLen >> 3);
 

tb/sw/src/SlvMain.c

@@ -3,7 +3,6 @@
 // #include "uart.h"
 // #include "gpio.h"
 // #include "timer.h"
-#include "custom_ops.S"
 
 
 volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
@@ -26,6 +25,37 @@ volatile uint32_t *ReadIsLast       = (uint32_t*) ( 0x408);
 
 
 
+
+
+
+
+
+
+volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
+volatile uint32_t *plic_enable_0_31  = (uint32_t*)( 0xc000000U + 0X002000 );
+volatile uint32_t *plic_claim        = (uint32_t*)( 0xc000000U + 0X200004 );
+
+uint32_t flag_intTxEnd = 0;
+uint32_t flag_intRxError = 0;
+uint32_t flag_intRxStart = 0;
+uint32_t flag_intRxEnd = 0;
+
+
+void trap_entry(){
+	if( *plic_claim == 3 ){
+		flag_intTxEnd = 1;
+	} else if( *plic_claim == 4 ){
+		flag_intRxError = 1;
+	} else if( *plic_claim == 5 ){
+		flag_intRxStart = 1;
+	} else if( *plic_claim == 6 ){
+		flag_intRxEnd = 1;
+	}
+	return;
+}
+
+
+	 
 // static inline void error() {
 //     while(1);
 // }

tb/sw/src/mstStartup.S

@@ -1,30 +1,59 @@
 
 
-#include "custom_ops.S"
-
 
 .extern main
+.extern trap_entry
 .globl _prog_start
 .section .text.init
 
 
 _prog_start:
-	li sp, 0x40001000
+
+	la t0, trap_entry
+	csrw mtvec, t0
+
+	li x1,  0
+	li x2,  0
+	li x3,  0
+	li x4,  0
+	li x5,  0
+	li x6,  0
+	li x7,  0
+	li x8,  0
+	li x9,  0
+	li x10, 0
+	li x11, 0
+	li x12, 0
+	li x13, 0
+	li x14, 0
+	li x15, 0
+	li x16, 0
+	li x17, 0
+	li x18, 0
+	li x19, 0
+	li x20, 0
+	li x21, 0
+	li x22, 0
+	li x23, 0
+	li x24, 0
+	li x25, 0
+	li x26, 0
+	li x27, 0
+	li x28, 0
+	li x29, 0
+	li x30, 0
+	li x31, 0
+
+	li sp, 0x40011000
 	call main
 
 	ecall
 
 
 
-
+# .balign 32
-
+# .section .trap_entry, "ax", %progbits
-
+# trap_entry:
-
-
-
-.balign 32
-.section .trap_entry, "ax", %progbits
-trap_entry:
 
 
 

tb/sw/src/slvStartup.S

@@ -1,24 +1,60 @@
 
 
-#include "custom_ops.S"
 
 
 .extern main
+.extern trap_entry
+
 .globl _prog_start
 .section .text.init
 
 
 _prog_start:
-	li sp, 0x40001000
 
+	la t0, trap_entry
+	csrw mtvec, t0
+
+	li x1,  0
+	li x2,  0
+	li x3,  0
+	li x4,  0
+	li x5,  0
+	li x6,  0
+	li x7,  0
+	li x8,  0
+	li x9,  0
+	li x10, 0
+	li x11, 0
+	li x12, 0
+	li x13, 0
+	li x14, 0
+	li x15, 0
+	li x16, 0
+	li x17, 0
+	li x18, 0
+	li x19, 0
+	li x20, 0
+	li x21, 0
+	li x22, 0
+	li x23, 0
+	li x24, 0
+	li x25, 0
+	li x26, 0
+	li x27, 0
+	li x28, 0
+	li x29, 0
+	li x30, 0
+	li x31, 0
+
+	li sp, 0x40011000
 	call main
 
 	ecall
 
 
-.balign 32
+# .balign 32
-.section .trap_entry, "ax", %progbits
+# .section .trap_entry, "ax", %progbits
-trap_entry:
+# trap_entry:
 
 	# io.interrupt(0) := intTxError
 	# io.interrupt(1) := intRxError

tb/verilator/SimTop.v

@@ -332,10 +332,11 @@ reg [7:0] mem3 [0:200000];
 
 localparam DP = 8192;
 integer i;
+
+
 initial begin
 
 #20
-
 	// if ( $value$plusargs("%s",testName) ) begin
 	// 	$display("%s",testName);
 	//   $readmemh(testName, mem);		
@@ -353,19 +354,17 @@ initial begin
     else begin
       `MEM0[i] = 32'h0;
     end
+
+    $display("%x",`MEM0[i]);
 	end
 
   $readmemh("./tb/sw/build/slvTest.verilog", mem1);
 	for ( i = 0; i < DP; i = i + 1 ) begin
     if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
       `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
-      `MEM2[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
-      `MEM3[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
     end
     else begin
       `MEM1[i] = 32'h0;
-      `MEM2[i] = 32'h0;
-      `MEM3[i] = 32'h0;
     end
 	end
 

tb/verilator/sim_main.cpp

@@ -99,14 +99,14 @@ int main(int argc, char **argv, char **env) {
 		return -1;
 	}
 
-	char * temp[2];
+	// char * temp[2];
-	char cmd[64] = "+";
+	// char cmd[64] = "+";
-	strcat(cmd, img);
+	// strcat(cmd, img);
-	strcat(cmd, ".verilog");
+	// strcat(cmd, ".verilog");
-	temp[0] = "Verilated";
+	// temp[0] = "Verilated";
-	temp[1] = cmd;
+	// temp[1] = cmd;
-	char **argv_temp = temp;
+	// char **argv_temp = temp;
-	Verilated::commandArgs(2, argv_temp);		
+	// Verilated::commandArgs(2, argv_temp);