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无法初始化sram

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RuigeLee
2025-01-15 15:44:29 +08:00
parent 074321ae58
commit 8236d45154
7 changed files with 218 additions and 75 deletions
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9
tb/verilator/SimTop.v
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@@ -332,10 +332,11 @@ reg [7:0] mem3 [0:200000];
localparam DP = 8192;
integer i;
initial begin
#20
// if ( $value$plusargs("%s",testName) ) begin
// $display("%s",testName);
// $readmemh(testName, mem);
@@ -353,19 +354,17 @@ initial begin
else begin
`MEM0[i] = 32'h0;
end
$display("%x",`MEM0[i]);
end
$readmemh("./tb/sw/build/slvTest.verilog", mem1);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
`MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
`MEM2[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
`MEM3[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
end
else begin
`MEM1[i] = 32'h0;
`MEM2[i] = 32'h0;
`MEM3[i] = 32'h0;
end
end