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无法初始化sram

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This commit is contained in:
RuigeLee
2025-01-15 15:44:29 +08:00
parent 074321ae58
commit 8236d45154
7 changed files with 218 additions and 75 deletions
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129
tb/sw/src/MstMain.c
View File

@@ -5,8 +5,29 @@
// #include "timer.h"
#include "tl2cdr.h"
volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
uint32_t flag_intTxEnd = 0;
uint32_t flag_intRxError = 0;
uint32_t flag_intRxStart = 0;
uint32_t flag_intRxEnd = 0;
void trap_entry(){
if( *plic_claim == 3 ){
flag_intTxEnd = 1;
} else if( *plic_claim == 4 ){
flag_intRxError = 1;
} else if( *plic_claim == 5 ){
flag_intRxStart = 1;
} else if( *plic_claim == 6 ){
flag_intRxEnd = 1;
}
return;
}
@@ -40,9 +61,12 @@ void main()
uint32_t led = 0;
*plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6;
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 0;
register uint32_t flag;
asm volatile ( //timer 2s
@@ -75,26 +99,34 @@ void main()
}
//等待发送完成标志
asm volatile (
"1:\n"
"andi %0, sp, 0x01\n"
"beqz %0, 1b\n"
"andi sp, sp, 0xFE\n"
:"+r"(flag)
);
// asm volatile (
// "1:\n"
// "andi %0, sp, 0x01\n"
// "beqz %0, 1b\n"
// "andi sp, sp, 0xFE\n"
// :"+r"(flag)
// );
while( !flag_intTxEnd );
flag_intTxEnd = 0;
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 1; //方向切换上行
//接收第一个包
asm volatile (
"1:\n"
"andi %0, sp, 0x04\n"
"beqz %0, 1b\n"
"andi sp, sp, 0xFB\n"
:"+r"(flag)
);
// asm volatile (
// "1:\n"
// "andi %0, sp, 0x04\n"
// "beqz %0, 1b\n"
// "andi sp, sp, 0xFB\n"
// :"+r"(flag)
// );
while(!flag_intRxStart);
flag_intRxStart = 0;
readDat = *cdr_rxFifo;
@@ -105,44 +137,57 @@ void main()
//接收第二个包
// asm volatile (
// "andi %0, sp, 0x08\n"
// "1:\n"
// "bnez %0, 1b\n" //error //速度不够，不校验
// :"+r"(flag),
// );
// asm volatile (
// "andi %0, sp, 0x08\n"
// "1:\n"
// "bnez %0, 1b\n" //error //速度不够，不校验
// :"+r"(flag),
// );
if( flag_intRxError ){
while(1);
}
uint32_t temp = *cdr_rxFifo;
//上行转发负载
for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
register uint32_t upData;
asm volatile (
"andi %0, sp, 0x80\n"
"1:\n"
"bnez %0, 1b\n" //error 速度不够，不再检查接收
"lw %1, 0x01c(x0)\n"
:"+r"(flag), "+r"(upData)
);
if( flag_intRxError ){
while(1);
}
// register uint32_t upData;
// asm volatile (
// "andi %0, sp, 0x80\n"
// "1:\n"
// "bnez %0, 1b\n" //error 速度不够，不再检查接收
// "lw %1, 0x01c(x0)\n"
// :"+r"(flag), "+r"(upData)
// );
}
//CRC
asm volatile (
"andi %0, sp, 0x08\n"
"1:\n"
"bnez %0, 1b\n" //error
:"+r"(flag)
);
if( flag_intRxError ){
while(1);
}
// asm volatile (
// "andi %0, sp, 0x08\n"
// "1:\n"
// "bnez %0, 1b\n" //error
// :"+r"(flag)
// );
uint32_t crc = *cdr_rxFifo; //CRC
//等待接收完成标志
asm volatile (
"1:\n"
"andi %0, sp, 0x08\n"
"beqz %0, 1b\n"
"andi sp, sp, 0xF7\n"
:"+r"(flag)
);
// asm volatile (
// "1:\n"
// "andi %0, sp, 0x08\n"
// "beqz %0, 1b\n"
// "andi sp, sp, 0xF7\n"
// :"+r"(flag)
// );
while(!flag_intRxEnd);
flag_intRxEnd = 0;
totNum = (upRecvLen >> 3);

32
tb/sw/src/SlvMain.c
View File

@@ -3,7 +3,6 @@
// #include "uart.h"
// #include "gpio.h"
// #include "timer.h"
#include "custom_ops.S"
volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
@@ -25,6 +24,37 @@ volatile uint32_t *ReadIsLast = (uint32_t*) ( 0x408);
volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
uint32_t flag_intTxEnd = 0;
uint32_t flag_intRxError = 0;
uint32_t flag_intRxStart = 0;
uint32_t flag_intRxEnd = 0;
void trap_entry(){
if( *plic_claim == 3 ){
flag_intTxEnd = 1;
} else if( *plic_claim == 4 ){
flag_intRxError = 1;
} else if( *plic_claim == 5 ){
flag_intRxStart = 1;
} else if( *plic_claim == 6 ){
flag_intRxEnd = 1;
}
return;
}
// static inline void error() {
// while(1);

53
tb/sw/src/mstStartup.S
View File

@@ -1,30 +1,59 @@
#include "custom_ops.S"
.extern main
.extern trap_entry
.globl _prog_start
.section .text.init
_prog_start:
li sp, 0x40001000
la t0, trap_entry
csrw mtvec, t0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
li sp, 0x40011000
call main
ecall
.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
# .balign 32
# .section .trap_entry, "ax", %progbits
# trap_entry:

46
tb/sw/src/slvStartup.S
View File

@@ -1,24 +1,60 @@
#include "custom_ops.S"
.extern main
.extern trap_entry
.globl _prog_start
.section .text.init
_prog_start:
li sp, 0x40001000
la t0, trap_entry
csrw mtvec, t0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
li sp, 0x40011000
call main
ecall
.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
# .balign 32
# .section .trap_entry, "ax", %progbits
# trap_entry:
# io.interrupt(0) := intTxError
# io.interrupt(1) := intRxError