无法初始化sram

Makefile

@@ -38,6 +38,7 @@ VSimTop:
 	-y ${PWD}/tb/verilator/ \
 	--top-module SimTop \
 	--trace-fst \
+	--no-timing \
 	--cc ./tb/verilator/SimTop.v  \
 	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
 	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
@@ -52,6 +53,7 @@ VSimTop:
 	-j 30
 
 
+
 test:
 	./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest
 
@@ -69,6 +71,7 @@ sw:
 
 	riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
 	-I ./tb/sw/ -I ./tb/sw/src \
+	-I ./tb/sw/tl2cdr \
 	-c ./tb/sw/src/mstMain.c \
 	-o ./tb/sw/build/mstMain.o
 
@@ -88,12 +91,13 @@ sw:
 	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
 
 	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.verilog
-	sed -i 's/@800/@000/g' ./tb/sw/build/mstTest.verilog
+	sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
 
 
 
 	riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
 	-I ./tb/sw/ -I ./tb/sw/src \
+	-I ./tb/sw/tl2cdr \
 	-c ./tb/sw/src/slvMain.c \
 	-o ./tb/sw/build/slvMain.o
 
@@ -118,7 +122,7 @@ sw:
 	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
 
 	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.verilog
-	sed -i 's/@800/@000/g' ./tb/sw/build/slvTest.verilog
+	sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
 
 	python3 ./tb/sw/bin_to_hex.py
 	python3 ./tb/sw/bin_to_coe.py