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remove tx retry

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This commit is contained in:
RuigeLee
2023-10-25 15:21:43 +08:00
parent 8fad6fc9cb
commit 811c540b6b
7 changed files with 17 additions and 121 deletions
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21
src/main/scala/Switch/mac/MAC.scala
View File

@@ -85,7 +85,6 @@ val TxStartFrm = Wire(Bool())
val TxEndFrm = Wire(Bool())
val TxUsedData = Wire(Bool())
val TxData = Wire(UInt(8.W))
val TxRetry = Wire(Bool())
val TxAbort = Wire(Bool())
val TxDone = Wire(Bool())
val TPauseRq = Wire(Bool())
@@ -94,7 +93,6 @@ dontTouch(TxStartFrm)
dontTouch(TxEndFrm )
dontTouch(TxUsedData)
dontTouch(TxData )
dontTouch(TxRetry )
dontTouch(TxAbort )
dontTouch(TxDone )
dontTouch(TPauseRq )
@@ -163,8 +161,6 @@ val r_IPGR2 = Wire(UInt(7.W))
val r_CollValid = Wire(UInt(6.W))
val r_TxPauseTV = Wire(UInt(16.W))
val r_TxPauseRq = Wire(Bool())
val r_MaxRet = Wire(UInt(4.W))
val r_NoBckof = Wire(Bool())
val r_ExDfrEn = Wire(Bool())
val r_TxFlow = Wire(Bool())
val r_IFG = Wire(Bool())
@@ -224,8 +220,6 @@ dontTouch(r_IPGR2 )
dontTouch(r_CollValid )
dontTouch(r_TxPauseTV )
dontTouch(r_TxPauseRq )
dontTouch(r_MaxRet )
dontTouch(r_NoBckof )
dontTouch(r_ExDfrEn )
dontTouch(r_TxFlow )
dontTouch(r_IFG )
@@ -294,7 +288,6 @@ r_CrcEn := io.cfg.r_CrcEn
r_DlyCrcEn := io.cfg.r_DlyCrcEn
r_FullD := io.cfg.r_FullD
r_ExDfrEn := io.cfg.r_ExDfrEn
r_NoBckof := io.cfg.r_NoBckof
r_LoopBck := io.cfg.r_LoopBck
r_IFG := io.cfg.r_IFG
r_NoPre := io.cfg.r_NoPre
@@ -307,7 +300,6 @@ r_IPGR1 := io.cfg.r_IPGR1
r_IPGR2 := io.cfg.r_IPGR2
r_MinFL := io.cfg.r_MinFL
r_MaxFL := io.cfg.r_MaxFL
r_MaxRet := io.cfg.r_MaxRet
r_CollValid := io.cfg.r_CollValid
r_TxFlow := io.cfg.r_TxFlow
r_RxFlow := io.cfg.r_RxFlow
@@ -340,8 +332,6 @@ val ReceivedPacketGood = Wire(Bool())
val ReceivedLengthOK = Wire(Bool())
val LatchedCrcError = Wire(Bool())
val RxLateCollision = Wire(Bool())
val RetryCntLatched = Wire(UInt(4.W))
val RetryCnt = Wire(UInt(4.W))
val StartTxAbort = Wire(Bool())
val MaxCollisionOccured = Wire(Bool())
val RetryLimit = Wire(Bool())
@@ -361,8 +351,6 @@ dontTouch(ReceivedPacketGood )
dontTouch(ReceivedLengthOK )
dontTouch(LatchedCrcError )
dontTouch(RxLateCollision )
dontTouch(RetryCntLatched )
dontTouch(RetryCnt )
dontTouch(StartTxAbort )
dontTouch(MaxCollisionOccured )
dontTouch(RetryLimit )
@@ -460,20 +448,16 @@ txethmac.io.IPGT := r_IPGT
txethmac.io.IPGR1 := r_IPGR1
txethmac.io.IPGR2 := r_IPGR2
txethmac.io.CollValid := r_CollValid
txethmac.io.MaxRet := r_MaxRet
txethmac.io.NoBckof := r_NoBckof
txethmac.io.ExDfrEn := r_ExDfrEn
io.mii.mtxd_pad_o := txethmac.io.MTxD
io.mii.mtxen_pad_o := txethmac.io.MTxEn
io.mii.mtxerr_pad_o := txethmac.io.MTxErr
TxDoneIn := txethmac.io.TxDone
TxRetry := txethmac.io.TxRetry
TxAbortIn := txethmac.io.TxAbort
TxUsedDataIn := txethmac.io.TxUsedData
WillTransmit := txethmac.io.WillTransmit
ResetCollision := txethmac.io.ResetCollision
RetryCnt := txethmac.io.RetryCnt
StartTxDone := txethmac.io.StartTxDone
StartTxAbort := txethmac.io.StartTxAbort
MaxCollisionOccured := txethmac.io.MaxCollisionOccured
@@ -592,7 +576,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val wishbone = Module(new MacTileLink)
wishbone.io.RetryCntLatched := RetryCntLatched
wishbone.io.RetryLimit := RetryLimit
wishbone.io.LateCollLatched := LateCollLatched
wishbone.io.DeferLatched := DeferLatched
@@ -635,7 +618,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macstatus.io.r_HugEn := r_HugEn
macstatus.io.StartTxDone := StartTxDone
macstatus.io.StartTxAbort := StartTxAbort
macstatus.io.RetryCnt := RetryCnt
macstatus.io.MTxClk := io.mii.mtx_clk_pad_i
macstatus.io.MaxCollisionOccured := MaxCollisionOccured
macstatus.io.LateCollision := LateCollision
@@ -656,7 +638,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
DribbleNibble := macstatus.io.DribbleNibble
ReceivedPacketTooBig := macstatus.io.ReceivedPacketTooBig
LoadRxStatus := macstatus.io.LoadRxStatus
RetryCntLatched := macstatus.io.RetryCntLatched
RetryLimit := macstatus.io.RetryLimit
LateCollLatched := macstatus.io.LateCollLatched
DeferLatched := macstatus.io.DeferLatched
@@ -705,11 +686,9 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
wishbone.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxUsedData := TxUsedData
macTileLinkTx.io.TxRetry := TxRetry
macTileLinkTx.io.TxAbort := TxAbort
macTileLinkTx.io.TxDone := TxDone
wishbone.io.TxRetrySync := ShiftRegister( TxRetry, 2, false.B, true.B )
wishbone.io.TxAbortSync := ShiftRegister( TxAbort, 2, false.B, true.B )
wishbone.io.TxDoneSync := ShiftRegister( TxDone, 2, false.B, true.B )

3
src/main/scala/Switch/mac/MacStatus.scala
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@@ -27,7 +27,6 @@ class MacStatusIO extends Bundle{
val r_HugEn = Input(Bool())
val StartTxDone = Input(Bool())
val StartTxAbort = Input(Bool())
val RetryCnt = Input(UInt(4.W))
val MTxClk = Input(Bool())
val MaxCollisionOccured = Input(Bool())
val LateCollision = Input(Bool())
@@ -48,7 +47,6 @@ class MacStatusIO extends Bundle{
val DribbleNibble = Output(Bool())
val ReceivedPacketTooBig = Output(Bool())
val LoadRxStatus = Output(Bool())
val RetryCntLatched = Output(UInt(4.W))
val RetryLimit = Output(Bool())
val LateCollLatched = Output(Bool())
val DeferLatched = Output(Bool())
@@ -127,7 +125,6 @@ class MacStatus extends RawModule{
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val RetryCntLatched = RegEnable( io.RetryCnt, 0.U(4.W), io.StartTxDone | io.StartTxAbort); io.RetryCntLatched := RetryCntLatched
val RetryLimit = RegEnable( io.MaxCollisionOccured, false.B, io.StartTxDone | io.StartTxAbort ); io.RetryLimit := RetryLimit // Latched Retransmission limit
val LateCollLatched = RegEnable( io.LateCollision, false.B, io.StartTxDone | io.StartTxAbort); io.LateCollLatched := LateCollLatched // Latched Late Collision

10
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -25,7 +25,6 @@ class MacTileLinkTxIO extends Bundle{
val TxData = Output(UInt(8.W)) // Transmit packet data byte
val TxUsedData = Input(Bool()) // Transmit packet used data
val TxRetry = Input(Bool()) // Transmit packet retry
val TxAbort = Input(Bool()) // Transmit packet abort
val TxDone = Input(Bool()) // Transmission ended
@@ -48,12 +47,11 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
// Generating delayed signals
val TxAbort_q = RegNext( io.TxAbort, false.B)
val TxRetry_q = RegNext( io.TxRetry, false.B)
val TxUsedData_q = RegNext( io.TxUsedData, false.B)
// Changes for tx occur every second clock. Flop is used for this manner.
val Flop = RegInit(false.B)
when( io.TxDone | io.TxAbort | TxRetry_q){
when( io.TxDone | io.TxAbort){
Flop := false.B
} .elsewhen ( io.TxUsedData ){
Flop := ~Flop
@@ -61,19 +59,19 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
when( io.txReq.valid & io.txReq.bits.isStart ){
TxStartFrm := true.B
} .elsewhen(TxUsedData_q | io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q) ){
} .elsewhen(TxUsedData_q | io.TxAbort & (~TxAbort_q) ){
TxStartFrm := false.B
}
// Indication of the last word
when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
when( (TxEndFrm | io.TxAbort) & Flop ){
LastWord := false.B
} .elsewhen( io.txReq.fire ){
LastWord := io.txReq.bits.isLast
}
// Tx end frame generation
when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
when(Flop & TxEndFrm | io.TxAbort){
TxEndFrm := false.B
} .elsewhen(Flop & LastWord){
TxEndFrm := true.B

14
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -36,7 +36,6 @@ abstract class MacTileLinkBase() extends Module{
// Tx Status signals
val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
val LateCollLatched = Input(Bool()) // Late collision occured
val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent)
@@ -49,7 +48,6 @@ abstract class MacTileLinkBase() extends Module{
val BlockingTxStatusWrite = Output(Bool())
val TxUsedData = Input(Bool()) // Transmit packet used data
val TxRetrySync = Input(Bool())
val TxAbortSync = Input(Bool()) // Transmit packet abort
val TxDoneSync = Input(Bool()) // Transmission ended
@@ -75,7 +73,7 @@ abstract class MacTileLinkBase() extends Module{
io.rxEnq.ctrl.valid := rxBuffCtrlValid
io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
when( io.rxEnq.ctrl.fire ){
rxBuffCtrlValid := false.B
@@ -134,7 +132,6 @@ abstract class MacTileLinkBase() extends Module{
val TxLength = RegInit(0.U(16.W))
val LatchedTxLength = RegInit(0.U(16.W))
val txRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
@@ -151,7 +148,7 @@ abstract class MacTileLinkBase() extends Module{
when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
} .elsewhen(txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B
}
@@ -176,14 +173,13 @@ abstract class MacTileLinkBase() extends Module{
when( io.txDeq.resp.fire ){
txRespValid := false.B
} .elsewhen( txRetryPulse | txDonePulse | txAbortPulse ){
} .elsewhen( txDonePulse | txAbortPulse ){
txRespValid := true.B
txRespBits.RetryCntLatched := io.RetryCntLatched
txRespBits.RetryLimit := io.RetryLimit
txRespBits.LateCollLatched := io.LateCollLatched
txRespBits.DeferLatched := io.DeferLatched
txRespBits.CarrierSenseLost := io.CarrierSenseLost
txRespBits.isClear := txAbortPulse | txRetryPulse
txRespBits.isClear := txAbortPulse
}
@@ -195,7 +191,7 @@ abstract class MacTileLinkBase() extends Module{
when( io.txDeq.req.fire){
isTxBusy := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
} .elsewhen(txDonePulse | txAbortPulse){
isTxBusy := false.B
}

79
src/main/scala/Switch/mac/MacTx.scala
View File

@@ -23,19 +23,16 @@ class MacTxIO extends Bundle{
val IPGR2 = Input(UInt(7.W)) // Non back to back transmit inter packet gap parameter IPGR2 (from register)
val CollValid = Input(UInt(6.W)) // Valid collision window (from register)
val MaxRet = Input(UInt(4.W)) // Maximum retry number (from register)
val NoBckof = Input(Bool()) // No backoff (from register)
val ExDfrEn = Input(Bool()) // Excessive defferal enable (from register)
val MTxD = Output(UInt(4.W)) // Transmit nibble (to PHY)
val MTxEn = Output(Bool()) // Transmit enable (to PHY)
val MTxErr = Output(Bool()) // Transmit error (to PHY)
val TxDone = Output(Bool()) // Transmit packet done (to RISC)
val TxRetry = Output(Bool()) // Transmit packet retry (to RISC)
val TxAbort = Output(Bool()) // Transmit packet abort (to RISC)
val TxUsedData = Output(Bool()) // Transmit packet used data (to RISC)
val WillTransmit = Output(Bool()) // Will transmit (to RxEthMAC)
val ResetCollision = Output(Bool()) // Reset Collision (for synchronizing collision)
val RetryCnt = Output(UInt(4.W)) // Latched Retry Counter for tx status purposes
val StartTxDone = Output(Bool())
val StartTxAbort = Output(Bool())
val MaxCollisionOccured= Output(Bool())
@@ -57,7 +54,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val StartFCS = Wire(Bool())
val StartJam = Wire(Bool())
val StartDefer = Wire(Bool())
val StartBackoff = Wire(Bool())
@@ -73,9 +69,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val ExcessiveDefer = Wire(Bool())
val MaxFrame = Wire(Bool())
val RetryMax = Wire(Bool())
val RandomEq0 = Wire(Bool())
val RandomEqByteCnt = Wire(Bool())
val StateIPG = RegInit(false.B)
val StateIdle = RegInit(false.B)
@@ -85,7 +78,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val StateFCS = RegInit(false.B)
val StateJam = RegInit(false.B)
val StateJam_q = RegNext(StateJam, false.B)
val StateBackOff = RegInit(false.B)
val StateDefer = RegInit(true.B)
val Rule1 = RegInit(false.B)
@@ -97,7 +89,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
val NibCntEq7 = NibCnt === 7.U
val NibCntEq15 = NibCnt === 15.U
val RetryCnt = RegInit(0.U(4.W)); io.RetryCnt := RetryCnt
}
@@ -122,13 +113,10 @@ trait MacTxFSM { this: MacTxBase =>
StartJam := (io.Collision ) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
StartBackoff := StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~io.NoBckof
StartDefer :=
(StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) |
(StateIdle & io.CarrierSense) |
(StateJam & NibCntEq7 & (io.NoBckof | RandomEq0 | ~ColWindow | RetryMax)) |
(StateBackOff & (RandomEqByteCnt)) |
(StateJam & NibCntEq7) |
io.StartTxDone |
TooBig
@@ -166,18 +154,12 @@ trait MacTxFSM { this: MacTxBase =>
StateFCS := true.B
}
when(StartBackoff | StartDefer){
when(StartDefer){
StateJam := false.B
} .elsewhen(StartJam){
StateJam := true.B
}
when(StartDefer){
StateBackOff := false.B
} .elsewhen(StartBackoff){
StateBackOff := true.B
}
when(StartIPG){
StateDefer := false.B
} .elsewhen(StartDefer){
@@ -185,7 +167,7 @@ trait MacTxFSM { this: MacTxBase =>
}
// This sections defines which interpack gap rule to use
when(StateIdle | StateBackOff){
when(StateIdle){
Rule1 := false.B
} .elsewhen(StatePreamble | io.FullD){
Rule1 := true.B
@@ -201,7 +183,7 @@ trait MacTxCounter { this: MacTxBase =>
val IncrementNibCnt =
StateIPG | StatePreamble |
(StateData(1) | StateData(0)) |
StatePAD | StateFCS | StateJam | StateBackOff |
StatePAD | StateFCS | StateJam |
(StateDefer & ~ExcessiveDefer & io.TxStartFrm)
@@ -224,11 +206,9 @@ trait MacTxCounter { this: MacTxBase =>
val IncrementByteCnt =
(StateData(1) & ~ByteCntMax) |
(StateBackOff & (NibCnt(6,0) === 127.U)) |
((StatePAD | StateFCS) & NibCnt.extract(0) & ~ByteCntMax)
val ResetByteCnt =
StartBackoff |
(StateIdle & io.TxStartFrm) |
PacketFinished_q
@@ -309,44 +289,14 @@ trait MacTxCRC{ this: MacTxBase =>
}
trait MacTxRandom{ this: MacTxBase =>
val x = RegInit(0.U(10.W))
when(true.B){
x := Cat( x(8,0), ~(x.extract(2) ^ x.extract(9)) )
}
val RandomLatched = RegEnable(
Cat(
Mux( RetryCnt > 9.U, x.extract(9), 0.U(1.W)),
Mux( RetryCnt > 8.U, x.extract(8), 0.U(1.W)),
Mux( RetryCnt > 7.U, x.extract(7), 0.U(1.W)),
Mux( RetryCnt > 6.U, x.extract(6), 0.U(1.W)),
Mux( RetryCnt > 5.U, x.extract(5), 0.U(1.W)),
Mux( RetryCnt > 4.U, x.extract(4), 0.U(1.W)),
Mux( RetryCnt > 3.U, x.extract(3), 0.U(1.W)),
Mux( RetryCnt > 2.U, x.extract(2), 0.U(1.W)),
Mux( RetryCnt > 1.U, x.extract(1), 0.U(1.W)),
x.extract(0)
),
0.U(10.W),
StateJam & StateJam_q
)
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
RandomEq0 := RandomLatched === 0.U
RandomEqByteCnt := ByteCnt(9,0) === RandomLatched & (NibCnt(6,0).andR)
}
class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with MacTxRandom{
class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
val MTxD = RegInit(0.U(4.W)); io.MTxD := MTxD
val StopExcessiveDeferOccured = RegInit(false.B)
val StatusLatch = RegInit(false.B)
val TxUsedData = RegNext(StartData(0) | StartData(1), false.B); io.TxUsedData := TxUsedData
val TxDone = RegInit(false.B); io.TxDone := TxDone
val TxRetry = RegInit(false.B); io.TxRetry := TxRetry
val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
@@ -360,9 +310,8 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
TooBig := ~io.Collision & MaxFrame & (StateData(0) | StateFCS);
val StartTxRetry = StartJam & (ColWindow & ~RetryMax)
io.LateCollision := StartJam & ~ColWindow
io.MaxCollisionOccured := StartJam & ColWindow & RetryMax;
io.MaxCollisionOccured := StartJam & ColWindow;
StateSFD := StatePreamble & NibCntEq15;
io.StartTxAbort := TooBig | ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
@@ -398,13 +347,6 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
TxDone := true.B
}
// Transmit packet retry
when(io.TxStartFrm & ~StatusLatch){
TxRetry := false.B
} .elsewhen(StartTxRetry){
TxRetry := true.B
}
// Transmit packet abort
when(io.TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured){
@@ -413,15 +355,6 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
TxAbort := true.B
}
// Retry counter
when(ExcessiveDeferOccured | TooBig | io.StartTxDone
| StateJam & NibCntEq7 & (~ColWindow | RetryMax)){
RetryCnt := 0.U
}.elsewhen(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | io.NoBckof) | StateBackOff & RandomEqByteCnt){
RetryCnt := RetryCnt + 1.U
}
RetryMax := RetryCnt === io.MaxRet
when( true.B ){
MTxD := // Transmit nibble