上行转发写入正确

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -329,10 +329,12 @@ abstract class SlaveParserBase extends Module{
   io.sram_r.dataw := 0.U
   io.sram_r.enr := 
     upRecParser.io.stateNext === STATE_PAYLOAD_DATA
-    // ( isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 1.U | upSubMsgInfo(0).operator === 3.U)) |
-    // (~isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 1.U | upSubMsgInfo(1).operator === 3.U))
 
-  io.sram_r.addr := addrr
+
+  io.sram_r.addr := Mux1H(Seq(
+    ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
+    ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
+  ))
 
 
   //子报文下行发送

tb/shinTest/SlaveParserTb.v

@@ -283,14 +283,141 @@ initial begin
   @(posedge clock) #3 
   io_downIn_valid = 0;
   io_downIn_bits_tlast = 0;
+
+
+
+
+  #1000
+  #1000
+  #1000
+  #1000
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = 8'h20;
+
+  @( io_upIn_valid & io_upIn_ready)
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = 8'h00; //heeader length 512
+
+
+
+
+
+  for( integer i = 0; i < 8; i = i + 1 ) begin
+    if( i != 5 ) begin
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random; 
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'h0;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'd56;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random;
+
+      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
+        @(posedge clock) #3 
+        io_upIn_valid = 1;
+        io_upIn_bits_tdata = 8'ha5; //heeader length 512
+      end
+    end else begin //第5个子报文操作
+      io_sram_r_datar = 8'hec;
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'h0; 
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'hC; //3号设备 类型空
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'h00; //地址
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'h10; //地址
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'h30; //命令3 长度56
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = 8'd56; //长度56
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random; //工作计数
+
+      @(posedge clock) #3 
+      io_upIn_valid = 1;
+      io_upIn_bits_tdata = $random; //工作计数
+
+      for( integer j = 0; j < 64-8; j = j+ 1 ) begin
+        @(posedge clock) #3 
+        io_upIn_valid = 1;
+        io_upIn_bits_tdata = 8'h55; //heeader length 512
+      end
+    end
+  end
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = $random;
+  io_upIn_bits_tlast = 0;
+  io_upIn_bits_tuser = 0;
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = $random;
+  io_upIn_bits_tlast = 0;
+  io_upIn_bits_tuser = 0;
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = $random;
+  io_upIn_bits_tlast = 0;
+  io_upIn_bits_tuser = 0;
+
+  @(posedge clock) #3 
+  io_upIn_valid = 1;
+  io_upIn_bits_tdata = $random;
+  io_upIn_bits_tlast = 1;
+  io_upIn_bits_tuser = 0;
+
+  @(posedge clock) #3 
+  io_upIn_valid = 0;
+  io_upIn_bits_tlast = 0;
 end
 
 
 
 
-
-
-
-
 endmodule