From 8068a31e77c17e1e8a65dac4f747bf2269119133 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 29 Oct 2024 10:43:48 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8A=A0=E6=8C=82gpio=E7=BC=96=E8=AF=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/pico/BackSystem.scala | 53 ++++++++++++++--- .../scala/backBoard/pico/SimpleGpio.scala | 59 +++++++++++++++++++ 2 files changed, 105 insertions(+), 7 deletions(-) create mode 100644 src/main/scala/backBoard/pico/SimpleGpio.scala diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index afc65b0..3556b96 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -57,7 +57,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter managers = Seq(TLSlaveParameters.v1( address = Seq(AddressSet(0x40000000L, 0xffL)), regionType = RegionType.UNCACHED, - executable = true, + executable = false, supportsGet = TransferSizes(32/8, 32/8), supportsPutFull = TransferSizes(32/8, 32/8), supportsPutPartial = TransferSizes(32/8, 32/8) @@ -81,16 +81,22 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter // initBaudRate = BigInt(115200), // ), divinit = 0) ) - // val gpio = LazyModule(new TLGPIO(busWidthBytes = 4, params = GPIOParams( - // address = BigInt(0x60000000L), - // width = 16, - // ))) + val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1( + managers = Seq(TLSlaveParameters.v1( + address = Seq(AddressSet(0x60000000L, 0xffL)), + regionType = RegionType.UNCACHED, + executable = false, + supportsGet = TransferSizes(32/8, 32/8), + supportsPutFull = TransferSizes(32/8, 32/8), + supportsPutPartial = TransferSizes(32/8, 32/8) + )), + beatBytes = 32/8))) val xbar = TLXbar() xbar := coreClientNode cdrNode := xbar sram.node := xbar - + gpioNode := xbar @@ -105,10 +111,18 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame val uDatOut = Output(Bool()) val dDatIn = Input(Bool()) val dDatOut = Output(Bool()) + + val out = Output(UInt(32.W)) + val in = Input(UInt(32.W)) + + val isOnline = Output(Bool()) + val isLast = Input(Bool()) + val DCIn = Input(Bool()) } val ( core_bus, core_edge ) = outer.coreClientNode.out.head val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head + val ( gpio_bus, gpio_edge ) = outer.gpioNode.in.head val io: BackSysIO = IO(new BackSysIO) @@ -116,11 +130,18 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame val pico = Module(new Picorv32_tl(edge = core_edge)) val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) } + val gpio = Module(new SimpleGpio(gpio_edge)) + + // val trap = Output(Bool()) - pico.io.irq := Cat( cdr(1).io.interrupt.asUInt, cdr(0).io.interrupt.asUInt ) + pico.io.irq := Cat( io.DCIn, cdr(1).io.interrupt.asUInt, cdr(0).io.interrupt.asUInt ) // val eoi = Output(UInt(32.W)) + io.out := gpio.io.out + gpio.io.in := io.in + io.isOnline := gpio.io.isOnline + gpio.io.isLast := io.isLast @@ -133,6 +154,15 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame cdr(1).io.datIn := io.dDatIn io.dDatOut := cdr(1).io.datOut + io.out := gpio.io.out + + + + + + + + pico.io.tld.bits := core_bus.d.bits pico.io.tld.valid := core_bus.d.valid @@ -165,4 +195,13 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame + gpio.io.tla.valid := gpio_bus.a.valid + gpio.io.tla.bits := gpio_bus.a.bits + gpio_bus.a.ready := gpio.io.tla.ready + + gpio_bus.d.valid := gpio.io.tld.valid + gpio_bus.d.bits := gpio.io.tld.bits + gpio.io.tld.ready := gpio_bus.d.ready + + } \ No newline at end of file diff --git a/src/main/scala/backBoard/pico/SimpleGpio.scala b/src/main/scala/backBoard/pico/SimpleGpio.scala new file mode 100644 index 0000000..d86e7ac --- /dev/null +++ b/src/main/scala/backBoard/pico/SimpleGpio.scala @@ -0,0 +1,59 @@ +package BACK + +import chisel3._ +import chisel3.util._ + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + + +class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{ + class SimpleGpioIO extends Bundle{ + val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle))) + val tld = new DecoupledIO(new TLBundleD(edge.bundle)) + + val out = Output(UInt(32.W)) + val in = Input(UInt(32.W)) + + + val isOnline = Output(Bool()) + val isLast = Input(Bool()) + + } + + val io: SimpleGpioIO = IO(new SimpleGpioIO) + + val isWriteGpio = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isReadGpio = io.tla.fire & io.tla.bits.address(3,0) === "h0".U & ( io.tla.bits.opcode === 4.U ) + // val isWriteDir = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) ) + val isReadIsLast = io.tla.fire & io.tla.bits.address(3,0) === "h8".U & ( io.tla.bits.opcode === 4.U ) + + + io.isOnline := false.B + + val tldValid = RegInit(false.B) + val tlaInfo = Reg(new TLBundleA(edge.bundle)) + val isRead = Reg(Bool()) + + io.out := RegEnable( io.tla.bits.data, 0.U(32.W), isWriteGpio ) + + when( io.tld.fire ){ + tldValid := false.B + } .elsewhen( io.tla.fire ){ + tldValid := true.B + tlaInfo := io.tla.bits + isRead := io.tla.bits.opcode === 4.U + } + + io.tla.ready := true.B + io.tld.valid := tldValid + + when(isRead) { + io.tld.bits := edge.AccessAck(tlaInfo, + Mux( tlaInfo.address(3,0) === "h0".U, io.in, Mux( tlaInfo.address(3,0) === "h8".U, io.isLast, 0.U ) ) + ) + } .otherwise { + io.tld.bits := edge.AccessAck(tlaInfo) + } +} \ No newline at end of file