diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 98c8205..79caca3 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -15,26 +15,6 @@ class ManualParamBundle extends Bundle{
 
 abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown with BackBoardSlvUp{
 
-  // def STATUSWR_ADDR     : UInt = "h00".U //01
-  // def DATA_PERWR_ADDR   : UInt = "h02".U //03
-  // def DATA_SINWR_ADDR   : UInt = "h04".U //05
-
-
-  // def STATUSRD_ADDR     : UInt = "h00".U //01
-  // def DATA_PERRD_ADDR   : UInt = "h02".U //03
-  // def DATA_SINRD_ADDR   : UInt = "h04".U //05
-
-
-
-  // def VENDORID_ADDR     : UInt = "h10".U
-  // def MODULEID_ADDR     : UInt = "h12".U
-  // def HVERSION_ADDR     : UInt = "h14".U
-  // def SVERSION_ADDR     : UInt = "h16".U
-  // def BATCHNUM_ADDR     : UInt = "h18".U
-  // def SERIAL0_ADDR      : UInt = "h1a".U
-  // def SERIAL1_ADDR      : UInt = "h1c".U
-  // def SERIAL2_ADDR      : UInt = "h1e".U
-
   val param = IO(Input( new ManualParamBundle ))
 
   val statusPage = downReg(0)(3,0)
@@ -129,56 +109,49 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
   val in = IO(Input(UInt((8*gp).W)))
 
-  val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/32)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
+  val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(3.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
   val flitTrigger = Wire(Vec(9, Bool()))
 
   flitTrigger(0) := ~RegNext(flitTrigger(0))
 
-  // flitTrigger(1) := usTrigger
-
-  flitTrigger(1) := flitCnt(1) >= (256/32-1).U
+  flitTrigger(1) := flitCnt(1) === 7.U
   when( ~RegNext(usTrigger) & usTrigger ){
-    when( flitTrigger(1) ){
-      flitCnt(1) := 0.U
-    } .otherwise{
-      flitCnt(1) := flitCnt(1) + 1.U      
-    }
-
+    flitCnt(1) := flitCnt(1) + 1.U      
   }
 
-  flitTrigger(2) := flitCnt(2) === 1.U
+  flitTrigger(2) := flitCnt(2)
   when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
-    flitCnt(2) := flitCnt(2) + 1.U
+    flitCnt(2) := ~flitCnt(2)
   }
 
-  flitTrigger(3) := flitCnt(3) === 1.U
+  flitTrigger(3) := flitCnt(3)
   when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
-    flitCnt(3) := flitCnt(3) + 1.U
+    flitCnt(3) := ~flitCnt(3)
   }
 
-  flitTrigger(4) := flitCnt(4) === 1.U
+  flitTrigger(4) := flitCnt(4)
   when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
-    flitCnt(4) := flitCnt(4) + 1.U
+    flitCnt(4) := ~flitCnt(4)
   }
 
-  flitTrigger(5) := flitCnt(5) === 1.U
+  flitTrigger(5) := flitCnt(5)
   when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
-    flitCnt(5) := flitCnt(5) + 1.U
+    flitCnt(5) := ~flitCnt(5)
   }
 
-  flitTrigger(6) := flitCnt(6) === 1.U
+  flitTrigger(6) := flitCnt(6)
   when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
-    flitCnt(6) := flitCnt(6) + 1.U
+    flitCnt(6) := ~flitCnt(6)
   }
 
-  flitTrigger(7) := flitCnt(7) === 1.U
+  flitTrigger(7) := flitCnt(7)
   when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
-    flitCnt(7) := flitCnt(7) + 1.U
+    flitCnt(7) := ~flitCnt(7)
   }
 
-  flitTrigger(8) := flitCnt(8) === 1.U
+  flitTrigger(8) := flitCnt(8)
   when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
-    flitCnt(8) := flitCnt(8) + 1.U
+    flitCnt(8) := ~flitCnt(8)
   }
 
   for( j <- 0 until gp ) {
@@ -197,11 +170,12 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
 
       val flitter = RegInit(VecInit( Seq.fill(32){false.B}))
       val flitHi  = RegInit(0.U((log2Ceil(32)).W))
+      val shiftIn = RegNext( in(i+8*j) )
 
       ( 0 until 9 ).map{ k => 
         when( digitalFilter === k.U ){
           when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
-            flitter(0) := in(i+8*j)
+            flitter(0) := shiftIn
             (1 until 32).map{ k =>
               flitter(k) := flitter(k-1)
             }
@@ -214,16 +188,16 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
               flitHi := flitHi - 1.U
             }
 
-            when( flitHi >= 26.U ){
+            when( flitHi >= 25.U ){
               digitalIn(i) := true.B
             } .elsewhen( flitHi <= 6.U ){
               digitalIn(i) := false.B
             }      
 
-            val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )
+            // val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )
 
-            assert( flitHi <= 31.U )
-            assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
+            // assert( flitHi <= 31.U )
+            // assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
 
           }
         }