From d7146a786bf84fdbc0819b6a2b0e60dd0f5d19e5 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 19 Aug 2025 17:04:26 +0800 Subject: [PATCH 1/7] =?UTF-8?q?cdrout=20=E6=AF=8F128byte=E5=8F=91=E9=80=81?= =?UTF-8?q?=E6=97=A0=E6=84=8F=E4=B9=89=E2=80=9Cb0000000010=E2=80=9D?= =?UTF-8?q?=E7=94=A8=E4=BA=8E=E8=A7=A3=E9=94=81cdrin=E5=B9=B6=E9=87=8D?= =?UTF-8?q?=E6=96=B0=E4=B8=8A=E9=94=81=20=E9=9C=80=E8=A6=81=E9=85=8D?= =?UTF-8?q?=E5=B9=B3fifo=EF=BC=8C=E8=A6=86=E7=9B=96=E6=AF=8F=E4=B8=AA?= =?UTF-8?q?=E9=95=BF=E5=BA=A6=E7=AB=AF=EF=BC=8C=E9=95=BF=E5=BA=A6=E8=BE=B9?= =?UTF-8?q?=E7=BC=98=EF=BC=8C=E8=A7=A3=E9=94=81=E5=9C=A8crc=E4=BD=8D?= =?UTF-8?q?=E7=BD=AE=EF=BC=8C=E4=B8=8D=E5=90=8Cpreamble=E9=95=BF=E5=BA=A6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 12 +++++++----- src/main/scala/backBoard/ebus/CDROut.scala | 12 ++++++++---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 7fe74d6..8307909 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -110,12 +110,12 @@ trait CDRInMultiSample{ this: CDRInBase => (sampleReg_sync(i+0) & sampleReg_sync(i+1)) } - val clearCnt = Reg(UInt(4.W)) + val clearCnt = Reg(UInt(3.W)) val arbLock = Reg(UInt( clkNum.W )) val isLock = RegInit(false.B) when( sampleReg.reduce(_|_) === false.B ){ - when( clearCnt =/= 10.U ){ + when( clearCnt =/= 6.U ){ clearCnt := clearCnt + 1.U } } .otherwise{ @@ -132,7 +132,7 @@ trait CDRInMultiSample{ this: CDRInBase => isLock := true.B } } - } .elsewhen( clearCnt === 10.U ){ + } .elsewhen( clearCnt === 6.U ){ isLock := false.B } @@ -171,6 +171,7 @@ trait CDRInAxis{ this: CDRInBase => val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) val shiftData = Dualb4b5Decoder(checkSFD(9,0)) + val isReleaseLock = checkSFD(9,0) === "b0000000010".U val payloadLen = RegInit(0.U(12.W)) when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ @@ -206,8 +207,9 @@ trait CDRInAxis{ this: CDRInBase => when( stateCurr === STATE_HEADER ){ byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) assert( byteCnt <= (HeaderByte-1).U ) + assert(~isReleaseLock) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U ) + byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), Mux( isReleaseLock, byteCnt, byteCnt + 1.U ), 0.U ) assert( byteCnt <= ( payloadLen+ (4-1).U ) ) } } @@ -229,7 +231,7 @@ trait CDRInAxis{ this: CDRInBase => when( io.axis.fire ){ axis_valid := false.B - } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ + } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | (stateCurr === STATE_PAYLOAD & ~isReleaseLock) ) ){ axis_valid := true.B } diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 48d8cf9..6dfb5c6 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -35,7 +35,7 @@ class CDROut extends Module{ val bitCnt = Reg(UInt(4.W)) - val byteCnt = Reg(UInt(3.W)) //payload dont need to count + val byteCnt = Reg(UInt(7.W)) //payload 计数用于插入解锁位 val shiftData = RegInit(0.U(10.W)) @@ -47,7 +47,7 @@ class CDROut extends Module{ io.serDat := shiftData.extract(9) io.axis.ready := - bitCnt === 9.U & ( + bitCnt === 9.U & ~byteCnt.andR & ( (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | (stateCurr === STATE_PAYLOAD) ) @@ -71,7 +71,11 @@ class CDROut extends Module{ ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata), )) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - shiftData := Dualb4b5Encoder(io.axis.bits.tdata) + when( byteCnt.andR ){//全1用于提示接收解锁 + shiftData := "b0000000010".U + } .otherwise{ + shiftData := Dualb4b5Encoder(io.axis.bits.tdata) + } } } } @@ -87,7 +91,7 @@ class CDROut extends Module{ } } - when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ + when( (stateCurr === STATE_IDLE) ){ byteCnt := 0.U } .elsewhen( bitCnt === 9.U ){ byteCnt := byteCnt + 1.U From 94eb807bed40ba11df09c9ffc42904ff9ffbba0b Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 19 Aug 2025 18:48:50 +0800 Subject: [PATCH 2/7] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B,=E6=B5=8B=E8=AF=95=E5=BA=95=E5=B1=82?= =?UTF-8?q?=E5=88=86=E5=8C=85=E5=AF=B9=E9=BD=90=E6=9C=BA=E5=88=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 12 ++++++++++-- tb/shinTest/testcase/__init__.py | 3 ++- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index e14c493..ed25fe1 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1,7 +1,7 @@ #!/usr/bin/env python #encoding=utf-8 from pyutils import * -from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base +from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac if __name__ == '__main__': environment.bringup() @@ -10,7 +10,7 @@ if __name__ == '__main__': #add_tc_2_runlist(errorPkt.tc2()) #add_tc_2_runlist(errorPkt.tc3()) #add_tc_2_runlist(errorPkt.tc4()) - add_tc_2_runlist(errorPkt.tc5()) + #add_tc_2_runlist(errorPkt.tc5()) #add_tc_2_runlist(base.tc1()) #add_tc_2_runlist(base.tc2()) @@ -76,6 +76,14 @@ if __name__ == '__main__': #add_tc_2_runlist(watchdog.tc1()) #add_tc_2_runlist(watchdog.tc2()) + add_tc_2_runlist(mac.tc1()) + add_tc_2_runlist(mac.tc2()) + add_tc_2_runlist(mac.tc3()) + add_tc_2_runlist(mac.tc4()) + add_tc_2_runlist(mac.tc5()) + add_tc_2_runlist(mac.tc6()) + add_tc_2_runlist(mac.tc7()) + environment.teardown() gen_tc_runlist() diff --git a/tb/shinTest/testcase/__init__.py b/tb/shinTest/testcase/__init__.py index 6677ae7..0f518cb 100644 --- a/tb/shinTest/testcase/__init__.py +++ b/tb/shinTest/testcase/__init__.py @@ -5,4 +5,5 @@ from .errorPkt import * from .watchdog import * from .broadcast import * from .sync import * -from .environment import * \ No newline at end of file +from .environment import * +from .mac import * \ No newline at end of file From b9d255b7ce627de09eb8261d5a342355f1722b25 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 20 Aug 2025 12:55:49 +0800 Subject: [PATCH 3/7] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=BC=8F=E4=BC=A0?= =?UTF-8?q?=E7=9A=84=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/testcase/mac.py | 87 +++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 tb/shinTest/testcase/mac.py diff --git a/tb/shinTest/testcase/mac.py b/tb/shinTest/testcase/mac.py new file mode 100644 index 0000000..3f07e25 --- /dev/null +++ b/tb/shinTest/testcase/mac.py @@ -0,0 +1,87 @@ +from pyutils import * + + + +def test_pkt_size(tc_id, size): + genPkt = GenPkt() + + gen_file_def = "mac_tc%02d"%(tc_id, ) + sm_idx = 0 + tc_des = ("测试MAC的分包机制, %d = %d + 8(subheader+wkc) + 4(header) + 4(crc)\\n"%(size, size - 16) + ) + + + #------------------------------------------------------------------------- + #>>>>>>普通数据包 sm1，2个读 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + #genPkt.addSubPkt(0x02, 0, 0x0830, 0x2, 56, None) + genPkt.addSubPkt(0x01, 0, 0x00, 0xd, size - 16, None) + #genPkt.addSubPkt(0x03, 0, 0xc0, 0x0, 64, None) + #genPkt.addSubPkt(10, 2, 0x300, 0x2, 4, None) + #genPkt.addSubPkt(11, 1, 0x300, 0x2, 4, None) + sm_idx = 1 + + genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)) + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--清除中断") + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--读写包状态") + +genIFRwDataCode(0, 0x22, False, 2) + +genIFRwDataCode(0, 0x22, True, 2, [0xff, 0xff]) + +genIFRwDataCode(0, 0x22, False, 2) + + + +genTcEndFrameCode(gen_file_def)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + return gen_file_def + + +def tc1(): + return test_pkt_size(1, 127) + +def tc2(): + return test_pkt_size(2, 128) + +def tc3(): + return test_pkt_size(3, 129) + +def tc4(): + return test_pkt_size(4, 130) + +def tc5(): + return test_pkt_size(5, 131) + +def tc6(): + return test_pkt_size(6, 132) + +def tc7(): + return test_pkt_size(7, 133) \ No newline at end of file From 0291d445ca69ce5f122985fcec819b14eda75f53 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 20 Aug 2025 15:40:25 +0800 Subject: [PATCH 4/7] =?UTF-8?q?Revert=20"cdrout=20=E6=AF=8F128byte?= =?UTF-8?q?=E5=8F=91=E9=80=81=E6=97=A0=E6=84=8F=E4=B9=89=E2=80=9Cb00000000?= =?UTF-8?q?10=E2=80=9D=E7=94=A8=E4=BA=8E=E8=A7=A3=E9=94=81cdrin=E5=B9=B6?= =?UTF-8?q?=E9=87=8D=E6=96=B0=E4=B8=8A=E9=94=81"?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit d7146a786bf84fdbc0819b6a2b0e60dd0f5d19e5. --- src/main/scala/backBoard/ebus/CDRIn.scala | 12 +++++------- src/main/scala/backBoard/ebus/CDROut.scala | 12 ++++-------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 8307909..7fe74d6 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -110,12 +110,12 @@ trait CDRInMultiSample{ this: CDRInBase => (sampleReg_sync(i+0) & sampleReg_sync(i+1)) } - val clearCnt = Reg(UInt(3.W)) + val clearCnt = Reg(UInt(4.W)) val arbLock = Reg(UInt( clkNum.W )) val isLock = RegInit(false.B) when( sampleReg.reduce(_|_) === false.B ){ - when( clearCnt =/= 6.U ){ + when( clearCnt =/= 10.U ){ clearCnt := clearCnt + 1.U } } .otherwise{ @@ -132,7 +132,7 @@ trait CDRInMultiSample{ this: CDRInBase => isLock := true.B } } - } .elsewhen( clearCnt === 6.U ){ + } .elsewhen( clearCnt === 10.U ){ isLock := false.B } @@ -171,7 +171,6 @@ trait CDRInAxis{ this: CDRInBase => val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) val shiftData = Dualb4b5Decoder(checkSFD(9,0)) - val isReleaseLock = checkSFD(9,0) === "b0000000010".U val payloadLen = RegInit(0.U(12.W)) when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ @@ -207,9 +206,8 @@ trait CDRInAxis{ this: CDRInBase => when( stateCurr === STATE_HEADER ){ byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) assert( byteCnt <= (HeaderByte-1).U ) - assert(~isReleaseLock) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), Mux( isReleaseLock, byteCnt, byteCnt + 1.U ), 0.U ) + byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U ) assert( byteCnt <= ( payloadLen+ (4-1).U ) ) } } @@ -231,7 +229,7 @@ trait CDRInAxis{ this: CDRInBase => when( io.axis.fire ){ axis_valid := false.B - } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | (stateCurr === STATE_PAYLOAD & ~isReleaseLock) ) ){ + } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ axis_valid := true.B } diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index 6dfb5c6..48d8cf9 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -35,7 +35,7 @@ class CDROut extends Module{ val bitCnt = Reg(UInt(4.W)) - val byteCnt = Reg(UInt(7.W)) //payload 计数用于插入解锁位 + val byteCnt = Reg(UInt(3.W)) //payload dont need to count val shiftData = RegInit(0.U(10.W)) @@ -47,7 +47,7 @@ class CDROut extends Module{ io.serDat := shiftData.extract(9) io.axis.ready := - bitCnt === 9.U & ~byteCnt.andR & ( + bitCnt === 9.U & ( (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) | (stateCurr === STATE_PAYLOAD) ) @@ -71,11 +71,7 @@ class CDROut extends Module{ ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata), )) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - when( byteCnt.andR ){//全1用于提示接收解锁 - shiftData := "b0000000010".U - } .otherwise{ - shiftData := Dualb4b5Encoder(io.axis.bits.tdata) - } + shiftData := Dualb4b5Encoder(io.axis.bits.tdata) } } } @@ -91,7 +87,7 @@ class CDROut extends Module{ } } - when( (stateCurr === STATE_IDLE) ){ + when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){ byteCnt := 0.U } .elsewhen( bitCnt === 9.U ){ byteCnt := byteCnt + 1.U From 6d8edfd6cebbe817ad2a883f947aa95de64c8802 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 20 Aug 2025 19:08:51 +0800 Subject: [PATCH 5/7] =?UTF-8?q?=E9=94=81=E5=AE=9A=E5=90=8E=EF=BC=8C?= =?UTF-8?q?=E6=AF=8F16=E4=B8=AAcycle=20=EF=BC=8C=E6=88=96=E8=AE=B8?= =?UTF-8?q?=E6=9C=89bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 37 +++++++++++++++++++---- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 7fe74d6..5379e86 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -67,6 +67,7 @@ trait CDRInOverSample{ this: CDRInBase => trait CDRInMultiSample{ this: CDRInBase => val clkNum: Int = 16 + require( clkNum == 16 ) //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 @@ -111,7 +112,8 @@ trait CDRInMultiSample{ this: CDRInBase => } val clearCnt = Reg(UInt(4.W)) - val arbLock = Reg(UInt( clkNum.W )) + val checkCnt = Reg(UInt(4.W)) + val arbLock = Reg(UInt( (log2Ceil(clkNum)+1).W )) val isLock = RegInit(false.B) when( sampleReg.reduce(_|_) === false.B ){ @@ -122,25 +124,48 @@ trait CDRInMultiSample{ this: CDRInBase => clearCnt := 0.U } + when( sampleReg.reduce(_|_) === false.B ){ + checkCnt := 0.U + } .otherwise{ + checkCnt := checkCnt + 1.U + } //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 - when( ~isLock ){ + + for( i <- 0 + 4 until clkNum + 4 ){ + val j = clkNum + 4 - i -1 + val diff = Wire(UInt( (log2Ceil(clkNum)).W )) + diff := arbLock - j.U + when( flitReg(j) ^ flitReg(j+1) ){ + when( ~isLock ){ + arbLock := j.U + isLock := true.B + } .elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 + when( diff > 8.U ){ + arbLock := arbLock + 1.U + } .elsewhen( diff < 8.U ){ + arbLock := arbLock - 1.U + } + } + } + } + + when( ~isLock ){ for( i <- 0 until clkNum ){ val j = clkNum - i -1 when( flitReg(j) ^ flitReg(j+1) ){ - arbLock := "b1".U(clkNum.W) << j isLock := true.B } } - } .elsewhen( clearCnt === 10.U ){ + }.elsewhen( clearCnt === 10.U ){ isLock := false.B } val asyncSerDat = Mux1H( - (for { i <- 0 until clkNum } yield { - (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2)) + (for { i <- 4 until clkNum+4 } yield { + (arbLock === i.U) -> flitReg(i+(clkNum/2)) }) ) From 06996d69452649a1e2cd6f104ce3b7f561e53a74 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 21 Aug 2025 18:57:28 +0800 Subject: [PATCH 6/7] =?UTF-8?q?=E9=94=81=E5=AE=9A=E5=90=8E=E5=85=81?= =?UTF-8?q?=E8=AE=B8=E5=9C=A8=E6=AD=A3=E8=B4=9F3=E7=9B=B8=E4=BD=8D?= =?UTF-8?q?=E4=B9=8B=E9=97=B4=E6=A0=A1=E5=87=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 50 +++++++++++++---------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 5379e86..374cf21 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -113,7 +113,8 @@ trait CDRInMultiSample{ this: CDRInBase => val clearCnt = Reg(UInt(4.W)) val checkCnt = Reg(UInt(4.W)) - val arbLock = Reg(UInt( (log2Ceil(clkNum)+1).W )) + val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W )) + val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W )) val isLock = RegInit(false.B) when( sampleReg.reduce(_|_) === false.B ){ @@ -132,40 +133,45 @@ trait CDRInMultiSample{ this: CDRInBase => //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 - for( i <- 0 + 4 until clkNum + 4 ){ - val j = clkNum + 4 - i -1 - val diff = Wire(UInt( (log2Ceil(clkNum)).W )) - diff := arbLock - j.U - when( flitReg(j) ^ flitReg(j+1) ){ - when( ~isLock ){ - arbLock := j.U - isLock := true.B - } .elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 - when( diff > 8.U ){ - arbLock := arbLock + 1.U - } .elsewhen( diff < 8.U ){ - arbLock := arbLock - 1.U + // val diff = Wire(UInt( (log2Ceil(clkNum)).W )) + // diff := arbLock - j.U + when( ~isLock ){ + for( i <- 3 until 19 ){ + val j = 19 - i - 1 + when( flitReg(j) ^ flitReg(j+1) ){ + arbLock := j.U + arbCali := j.U + } + } + }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 + for( i <- 0 until 22 ){ + val j = 22 - i -1 + when( flitReg(j) ^ flitReg(j+1) ){ + when( (j.U < arbCali) && ((j+3).U >= arbLock) ){ + arbCali := arbCali - 1.U + } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){ + arbCali := arbCali + 1.U + } } } } - } - - when( ~isLock ){ - for( i <- 0 until clkNum ){ - val j = clkNum - i -1 + + when( ~isLock ){ + for( i <- 3 until 19 ){ + val j = 19 - i - 1 when( flitReg(j) ^ flitReg(j+1) ){ isLock := true.B } } - }.elsewhen( clearCnt === 10.U ){ + } .elsewhen( clearCnt === 10.U ){ isLock := false.B } val asyncSerDat = Mux1H( - (for { i <- 4 until clkNum+4 } yield { - (arbLock === i.U) -> flitReg(i+(clkNum/2)) + (for { i <- 0 until 22 } yield { + (arbCali === i.U) -> flitReg(i+(8)) }) ) From 0a0a7a771235859bec2a845bb506d387ede488a9 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 22 Aug 2025 14:24:41 +0800 Subject: [PATCH 7/7] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E8=A7=A3=E9=94=81?= =?UTF-8?q?=E6=9D=A1=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 374cf21..a9557f7 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -117,7 +117,7 @@ trait CDRInMultiSample{ this: CDRInBase => val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W )) val isLock = RegInit(false.B) - when( sampleReg.reduce(_|_) === false.B ){ + when( sampleReg_sync.reduce(_|_) === false.B ){ when( clearCnt =/= 10.U ){ clearCnt := clearCnt + 1.U } @@ -125,7 +125,7 @@ trait CDRInMultiSample{ this: CDRInBase => clearCnt := 0.U } - when( sampleReg.reduce(_|_) === false.B ){ + when( ~isLock ){ checkCnt := 0.U } .otherwise{ checkCnt := checkCnt + 1.U