diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 7fe74d6..a9557f7 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -67,6 +67,7 @@ trait CDRInOverSample{ this: CDRInBase => trait CDRInMultiSample{ this: CDRInBase => val clkNum: Int = 16 + require( clkNum == 16 ) //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 @@ -111,10 +112,12 @@ trait CDRInMultiSample{ this: CDRInBase => } val clearCnt = Reg(UInt(4.W)) - val arbLock = Reg(UInt( clkNum.W )) + val checkCnt = Reg(UInt(4.W)) + val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W )) + val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W )) val isLock = RegInit(false.B) - when( sampleReg.reduce(_|_) === false.B ){ + when( sampleReg_sync.reduce(_|_) === false.B ){ when( clearCnt =/= 10.U ){ clearCnt := clearCnt + 1.U } @@ -122,13 +125,41 @@ trait CDRInMultiSample{ this: CDRInBase => clearCnt := 0.U } + when( ~isLock ){ + checkCnt := 0.U + } .otherwise{ + checkCnt := checkCnt + 1.U + } //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 + + // val diff = Wire(UInt( (log2Ceil(clkNum)).W )) + // diff := arbLock - j.U + when( ~isLock ){ + for( i <- 3 until 19 ){ + val j = 19 - i - 1 + when( flitReg(j) ^ flitReg(j+1) ){ + arbLock := j.U + arbCali := j.U + } + } + }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 + for( i <- 0 until 22 ){ + val j = 22 - i -1 + when( flitReg(j) ^ flitReg(j+1) ){ + when( (j.U < arbCali) && ((j+3).U >= arbLock) ){ + arbCali := arbCali - 1.U + } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){ + arbCali := arbCali + 1.U + } + } + } + } + when( ~isLock ){ - for( i <- 0 until clkNum ){ - val j = clkNum - i -1 + for( i <- 3 until 19 ){ + val j = 19 - i - 1 when( flitReg(j) ^ flitReg(j+1) ){ - arbLock := "b1".U(clkNum.W) << j isLock := true.B } } @@ -139,8 +170,8 @@ trait CDRInMultiSample{ this: CDRInBase => val asyncSerDat = Mux1H( - (for { i <- 0 until clkNum } yield { - (arbLock === (1.U << i)) -> flitReg(i+(clkNum/2)) + (for { i <- 0 until 22 } yield { + (arbCali === i.U) -> flitReg(i+(8)) }) ) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 961f68b..37f91dd 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1,7 +1,7 @@ #!/usr/bin/env python #encoding=utf-8 from pyutils import * -from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base +from testcase import environment, readregs, ebmmu, errorPkt, watchdog, broadcast, sync, base, mac if __name__ == '__main__': environment.gen_slv_dev_num(4) @@ -79,6 +79,14 @@ if __name__ == '__main__': #add_tc_2_runlist(watchdog.tc1()) #add_tc_2_runlist(watchdog.tc2()) + add_tc_2_runlist(mac.tc1()) + add_tc_2_runlist(mac.tc2()) + add_tc_2_runlist(mac.tc3()) + add_tc_2_runlist(mac.tc4()) + add_tc_2_runlist(mac.tc5()) + add_tc_2_runlist(mac.tc6()) + add_tc_2_runlist(mac.tc7()) + environment.teardown() gen_tc_runlist() diff --git a/tb/shinTest/testcase/__init__.py b/tb/shinTest/testcase/__init__.py index 6677ae7..0f518cb 100644 --- a/tb/shinTest/testcase/__init__.py +++ b/tb/shinTest/testcase/__init__.py @@ -5,4 +5,5 @@ from .errorPkt import * from .watchdog import * from .broadcast import * from .sync import * -from .environment import * \ No newline at end of file +from .environment import * +from .mac import * \ No newline at end of file diff --git a/tb/shinTest/testcase/mac.py b/tb/shinTest/testcase/mac.py new file mode 100644 index 0000000..3f07e25 --- /dev/null +++ b/tb/shinTest/testcase/mac.py @@ -0,0 +1,87 @@ +from pyutils import * + + + +def test_pkt_size(tc_id, size): + genPkt = GenPkt() + + gen_file_def = "mac_tc%02d"%(tc_id, ) + sm_idx = 0 + tc_des = ("测试MAC的分包机制, %d = %d + 8(subheader+wkc) + 4(header) + 4(crc)\\n"%(size, size - 16) + ) + + + #------------------------------------------------------------------------- + #>>>>>>普通数据包 sm1，2个读 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + #genPkt.addSubPkt(0x02, 0, 0x0830, 0x2, 56, None) + genPkt.addSubPkt(0x01, 0, 0x00, 0xd, size - 16, None) + #genPkt.addSubPkt(0x03, 0, 0xc0, 0x0, 64, None) + #genPkt.addSubPkt(10, 2, 0x300, 0x2, 4, None) + #genPkt.addSubPkt(11, 1, 0x300, 0x2, 4, None) + sm_idx = 1 + + genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des)) + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--清除中断") + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--读写包状态") + +genIFRwDataCode(0, 0x22, False, 2) + +genIFRwDataCode(0, 0x22, True, 2, [0xff, 0xff]) + +genIFRwDataCode(0, 0x22, False, 2) + + + +genTcEndFrameCode(gen_file_def)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + return gen_file_def + + +def tc1(): + return test_pkt_size(1, 127) + +def tc2(): + return test_pkt_size(2, 128) + +def tc3(): + return test_pkt_size(3, 129) + +def tc4(): + return test_pkt_size(4, 130) + +def tc5(): + return test_pkt_size(5, 131) + +def tc6(): + return test_pkt_size(6, 132) + +def tc7(): + return test_pkt_size(7, 133) \ No newline at end of file