From 7f85f14d921d5802ee171dff242e888f608d00d8 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 23 May 2024 13:45:15 +0800
Subject: [PATCH] =?UTF-8?q?=E6=AF=8F=E6=AC=A1=E5=88=9D=E5=A7=8B=E5=8C=96?=
 =?UTF-8?q?=E5=BC=BA=E5=88=B6=E6=B8=85=E9=99=A4sync,trans,uni=E6=A0=87?=
 =?UTF-8?q?=E5=BF=97=E4=BD=8D?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 88aaf44..cce410f 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -292,6 +292,9 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       mirrorReg.io.enwB   := true.B
 
       ctrlInit    := false.B
+      ctrlSynch   := false.B
+      ctrlTransmit := false.B
+      ctrlUnicast := false.B
       interrupt   := true.B
 
     } .elsewhen( stateCur === 7.U ){