diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 88aaf44..cce410f 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -292,6 +292,9 @@ trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
       mirrorReg.io.enwB   := true.B
 
       ctrlInit    := false.B
+      ctrlSynch   := false.B
+      ctrlTransmit := false.B
+      ctrlUnicast := false.B
       interrupt   := true.B
 
     } .elsewhen( stateCur === 7.U ){