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maccontrol remove

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This commit is contained in:
RuigeLee
2023-10-25 17:52:43 +08:00
parent 1e6f2df9ae
commit 7f8536ec82
6 changed files with 61 additions and 646 deletions
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162
src/main/scala/Switch/mac/MAC.scala
View File

@@ -87,7 +87,6 @@ val TxUsedData = Wire(Bool())
val TxData = Wire(UInt(8.W))
val TxAbort = Wire(Bool())
val TxDone = Wire(Bool())
val TPauseRq = Wire(Bool())
dontTouch(TxStartFrm)
dontTouch(TxEndFrm )
@@ -95,9 +94,6 @@ dontTouch(TxUsedData)
dontTouch(TxData )
dontTouch(TxAbort )
dontTouch(TxDone )
dontTouch(TPauseRq )
val RstTxPauseRq = RegInit(false.B)
@@ -148,19 +144,14 @@ val r_DlyCrcEn = Wire(Bool())
val r_MaxFL = Wire(UInt(16.W))
val r_MinFL = Wire(UInt(16.W))
val DribbleNibble = Wire(Bool())
val r_MAC = Wire(UInt(48.W))
val LoadRxStatus = Wire(Bool())
val r_HASH0 = Wire(UInt(32.W))
val r_HASH1 = Wire(UInt(32.W))
val r_TxBDNum = Wire(UInt(8.W))
val r_IPGT = Wire(UInt(7.W))
val r_IPGR1 = Wire(UInt(7.W))
val r_IPGR2 = Wire(UInt(7.W))
val r_CollValid = Wire(UInt(6.W))
val r_TxPauseTV = Wire(UInt(16.W))
val r_TxPauseRq = Wire(Bool())
val r_ExDfrEn = Wire(Bool())
val r_TxFlow = Wire(Bool())
val r_IFG = Wire(Bool())
val TxB_IRQ = Wire(Bool())
val TxE_IRQ = Wire(Bool())
@@ -171,22 +162,9 @@ val r_Pad = Wire(Bool())
val r_CrcEn = Wire(Bool())
val r_FullD = Wire(Bool())
val r_NoPre = Wire(Bool())
val r_RxFlow = Wire(Bool())
val TxCtrlEndFrm = Wire(Bool())
val StartTxDone = Wire(Bool())
val SetPauseTimer = Wire(Bool())
val TxUsedDataIn = Wire(Bool())
val TxDoneIn = Wire(Bool())
val TxAbortIn = Wire(Bool())
val PerPacketPad = Wire(Bool())
val PadOut = Wire(Bool())
val PerPacketCrcEn = Wire(Bool())
val CrcEnOut = Wire(Bool())
val TxStartFrmOut = Wire(Bool())
val TxEndFrmOut = Wire(Bool())
val ReceivedPauseFrm = Wire(Bool())
val ControlFrmAddressOK = Wire(Bool())
val RxStatusWriteLatchedSync = Wire(Bool())
val LateCollision = Wire(Bool())
val DeferIndication = Wire(Bool())
val LateCollLatched = Wire(Bool())
@@ -205,19 +183,14 @@ dontTouch(r_DlyCrcEn )
dontTouch(r_MaxFL )
dontTouch(r_MinFL )
dontTouch(DribbleNibble )
dontTouch(r_MAC )
dontTouch(LoadRxStatus )
dontTouch(r_HASH0 )
dontTouch(r_HASH1 )
dontTouch(r_TxBDNum )
dontTouch(r_IPGT )
dontTouch(r_IPGR1 )
dontTouch(r_IPGR2 )
dontTouch(r_CollValid )
dontTouch(r_TxPauseTV )
dontTouch(r_TxPauseRq )
dontTouch(r_ExDfrEn )
dontTouch(r_TxFlow )
dontTouch(r_IFG )
dontTouch(TxB_IRQ )
dontTouch(TxE_IRQ )
@@ -228,22 +201,9 @@ dontTouch(r_Pad )
dontTouch(r_CrcEn )
dontTouch(r_FullD )
dontTouch(r_NoPre )
dontTouch(r_RxFlow )
dontTouch(TxCtrlEndFrm )
dontTouch(StartTxDone )
dontTouch(SetPauseTimer )
dontTouch(TxUsedDataIn )
dontTouch(TxDoneIn )
dontTouch(TxAbortIn )
dontTouch(PerPacketPad )
dontTouch(PadOut )
dontTouch(PerPacketCrcEn )
dontTouch(CrcEnOut )
dontTouch(TxStartFrmOut )
dontTouch(TxEndFrmOut )
dontTouch(ReceivedPauseFrm )
dontTouch(ControlFrmAddressOK )
dontTouch(RxStatusWriteLatchedSync )
dontTouch(LateCollision )
dontTouch(DeferIndication )
dontTouch(LateCollLatched )
@@ -255,9 +215,6 @@ dontTouch(CarrierSenseLost )
// val ethReg = Module(new MacReg(outer.configNode))
io.cfg.WCtrlDataStart := WCtrlDataStart
io.cfg.RStatStart := RStatStart
@@ -271,12 +228,9 @@ io.cfg.TxE_IRQ := TxE_IRQ
io.cfg.RxB_IRQ := RxB_IRQ
io.cfg.RxE_IRQ := RxE_IRQ
io.cfg.Busy_IRQ := Busy_IRQ
io.cfg.RstTxPauseRq := RstTxPauseRq
io.cfg.TxCtrlEndFrm := TxCtrlEndFrm
io.cfg.StartTxDone := StartTxDone
io.cfg.TxClk := io.mii.mtx_clk_pad_i
io.cfg.RxClk := io.mii.mrx_clk_pad_i
io.cfg.SetPauseTimer := SetPauseTimer
r_Pad := io.cfg.r_Pad
r_CrcEn := io.cfg.r_CrcEn
@@ -296,8 +250,6 @@ r_IPGR2 := io.cfg.r_IPGR2
r_MinFL := io.cfg.r_MinFL
r_MaxFL := io.cfg.r_MaxFL
r_CollValid := io.cfg.r_CollValid
r_TxFlow := io.cfg.r_TxFlow
r_RxFlow := io.cfg.r_RxFlow
r_MiiNoPre := io.cfg.r_MiiNoPre
r_ClkDiv := io.cfg.r_ClkDiv
r_WCtrlData := io.cfg.r_WCtrlData
@@ -306,11 +258,6 @@ r_ScanStat := io.cfg.r_ScanStat
r_RGAD := io.cfg.r_RGAD
r_FIAD := io.cfg.r_FIAD
r_CtrlData := io.cfg.r_CtrlData
r_MAC := io.cfg.r_MAC
r_TxBDNum := io.cfg.r_TxBDNum
r_TxPauseTV := io.cfg.r_TxPauseTV
r_TxPauseRq := io.cfg.r_TxPauseRq
@@ -320,11 +267,6 @@ val RxStartFrm = Wire(Bool())
val RxEndFrm = Wire(Bool())
val WillTransmit = Wire(Bool())
val ResetCollision = Wire(Bool())
val TxDataOut = Wire(UInt(8.W))
val WillSendControlFrame = Wire(Bool())
val ReceiveEnd = Wire(Bool())
val ReceivedPacketGood = Wire(Bool())
val ReceivedLengthOK = Wire(Bool())
val LatchedCrcError = Wire(Bool())
val RxLateCollision = Wire(Bool())
val StartTxAbort = Wire(Bool())
@@ -339,11 +281,6 @@ dontTouch(RxStartFrm )
dontTouch(RxEndFrm )
dontTouch(WillTransmit )
dontTouch(ResetCollision )
dontTouch(TxDataOut )
dontTouch(WillSendControlFrame)
dontTouch(ReceiveEnd )
dontTouch(ReceivedPacketGood )
dontTouch(ReceivedLengthOK )
dontTouch(LatchedCrcError )
dontTouch(RxLateCollision )
dontTouch(StartTxAbort )
@@ -353,49 +290,24 @@ dontTouch(StatePreamble )
dontTouch(StateData )
// Connecting MACControl
val maccontrol = Module(new MacControl)
maccontrol.io.MTxClk := io.mii.mtx_clk_pad_i
maccontrol.io.MRxClk := io.mii.mrx_clk_pad_i
maccontrol.io.asyncReset := io.asyncReset
maccontrol.io.TPauseRq := TPauseRq
maccontrol.io.TxDataIn := TxData
maccontrol.io.TxStartFrmIn := TxStartFrm
maccontrol.io.TxUsedDataIn := TxUsedDataIn
maccontrol.io.TxEndFrmIn := TxEndFrm
maccontrol.io.TxDoneIn := TxDoneIn
maccontrol.io.TxAbortIn := TxAbortIn
maccontrol.io.PadIn := r_Pad | PerPacketPad
maccontrol.io.CrcEnIn := r_CrcEn | PerPacketCrcEn
maccontrol.io.RxData := RxData
maccontrol.io.RxValid := RxValid
maccontrol.io.RxStartFrm := RxStartFrm
maccontrol.io.RxEndFrm := RxEndFrm
maccontrol.io.ReceiveEnd := ReceiveEnd
maccontrol.io.ReceivedPacketGood := ReceivedPacketGood
maccontrol.io.ReceivedLengthOK := ReceivedLengthOK
maccontrol.io.TxFlow := r_TxFlow
maccontrol.io.RxFlow := r_RxFlow
maccontrol.io.DlyCrcEn := r_DlyCrcEn
maccontrol.io.TxPauseTV := r_TxPauseTV
maccontrol.io.MAC := r_MAC
maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatchedSync
TxDataOut := maccontrol.io.TxDataOut
TxStartFrmOut := maccontrol.io.TxStartFrmOut
TxEndFrmOut := maccontrol.io.TxEndFrmOut
TxDone := maccontrol.io.TxDoneOut
TxAbort := maccontrol.io.TxAbortOut
TxUsedData := maccontrol.io.TxUsedDataOut
PadOut := maccontrol.io.PadOut
CrcEnOut := maccontrol.io.CrcEnOut
WillSendControlFrame := maccontrol.io.WillSendControlFrame
TxCtrlEndFrm := maccontrol.io.TxCtrlEndFrm
ReceivedPauseFrm := maccontrol.io.ReceivedPauseFrm
ControlFrmAddressOK := maccontrol.io.ControlFrmAddressOK
SetPauseTimer := maccontrol.io.SetPauseTimer
@@ -427,13 +339,13 @@ MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
txethmac.io.TxStartFrm := TxStartFrmOut
txethmac.io.TxEndFrm := TxEndFrmOut
txethmac.io.TxData := TxDataOut
txethmac.io.TxStartFrm := TxStartFrm
txethmac.io.TxEndFrm := TxEndFrm
txethmac.io.TxData := TxData
txethmac.io.CarrierSense := TxCarrierSense
txethmac.io.Collision := Collision
txethmac.io.Pad := PadOut
txethmac.io.CrcEn := CrcEnOut
txethmac.io.Pad := r_Pad | PerPacketPad
txethmac.io.CrcEn := r_CrcEn | PerPacketCrcEn
txethmac.io.FullD := r_FullD
txethmac.io.DlyCrcEn := r_DlyCrcEn
txethmac.io.MinFL := r_MinFL
@@ -447,9 +359,9 @@ txethmac.io.ExDfrEn := r_ExDfrEn
io.mii.mtxd_pad_o := txethmac.io.MTxD
io.mii.mtxen_pad_o := txethmac.io.MTxEn
io.mii.mtxerr_pad_o := txethmac.io.MTxErr
TxDoneIn := txethmac.io.TxDone
TxDone := txethmac.io.TxDone
TxAbortIn := txethmac.io.TxAbort
TxUsedDataIn := txethmac.io.TxUsedData
TxUsedData := txethmac.io.TxUsedData
WillTransmit := txethmac.io.WillTransmit
ResetCollision := txethmac.io.ResetCollision
StartTxDone := txethmac.io.StartTxDone
@@ -472,7 +384,6 @@ val RxStateIdle = Wire(Bool())
val RxStatePreamble = Wire(Bool())
val RxStateSFD = Wire(Bool())
val RxStateData = Wire(UInt(2.W))
val AddressMiss = Wire(Bool())
dontTouch(RxByteCnt )
@@ -483,7 +394,7 @@ dontTouch(RxStateIdle )
dontTouch(RxStatePreamble )
dontTouch(RxStateSFD )
dontTouch(RxStateData )
dontTouch(AddressMiss )
val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
@@ -493,10 +404,8 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
rxethmac.io.DlyCrcEn := r_DlyCrcEn
rxethmac.io.MaxFL := r_MaxFL
rxethmac.io.r_IFG := r_IFG
rxethmac.io.MAC := r_MAC
rxethmac.io.r_HASH0 := r_HASH0
rxethmac.io.r_HASH1 := r_HASH1
rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
RxData := rxethmac.io.RxData
RxValid := rxethmac.io.RxValid
@@ -510,7 +419,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
RxStatePreamble := rxethmac.io.StatePreamble
RxStateSFD := rxethmac.io.StateSFD
RxStateData := rxethmac.io.StateData
AddressMiss := rxethmac.io.AddressMiss
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
@@ -547,21 +456,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
// Synchronizing WillSendControlFrame to WB_CLK;
val WillSendControlFrame_sync = ShiftRegisters(WillSendControlFrame, 3, false.B, true.B)
when(true.B){
RstTxPauseRq := WillSendControlFrame_sync(1) & ~WillSendControlFrame_sync(2)
}
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
}
val wishbone = Module(new MacTileLink)
@@ -609,7 +503,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macstatus.io.MaxCollisionOccured := MaxCollisionOccured
macstatus.io.LateCollision := LateCollision
macstatus.io.DeferIndication := DeferIndication
macstatus.io.TxStartFrm := TxStartFrmOut
macstatus.io.TxStartFrm := TxStartFrm
macstatus.io.StatePreamble := StatePreamble
macstatus.io.StateData := StateData
macstatus.io.CarrierSense := CarrierSense_Tx2
@@ -617,9 +511,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macstatus.io.r_FullD := r_FullD
macstatus.io.RstDeferLatched := RstDeferLatched
ReceivedLengthOK := macstatus.io.ReceivedLengthOK
ReceiveEnd := macstatus.io.ReceiveEnd
ReceivedPacketGood := macstatus.io.ReceivedPacketGood
LatchedCrcError := macstatus.io.LatchedCrcError
RxLateCollision := macstatus.io.RxLateCollision
DribbleNibble := macstatus.io.DribbleNibble
@@ -731,7 +622,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
RxStatusWriteLatchedSync := fateRxRespPort.fire
macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )
macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B )
@@ -746,7 +636,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macTileLinkRx.io.RxLength := RxByteCnt
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
macTileLinkRx.io.RxStatusIn := Cat(ReceivedPauseFrm, AddressMiss, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
macTileLinkRx.io.RxStatusIn := Cat(false.B, false.B, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
wishbone.io.rxEnq <> io.rxEnq

411
src/main/scala/Switch/mac/MacControl.scala
View File

@@ -9,7 +9,6 @@ val MRxClk = Input(Bool()) // Receive clock (fro
val asyncReset = Input(AsyncReset())
val TPauseRq = Input(Bool()) // Transmit control frame (from host)
val TxDataIn = Input(UInt(8.W)) // Transmit packet data byte (from host)
val TxStartFrmIn = Input(Bool()) // Transmit packet start frame input (from host)
val TxUsedDataIn = Input(Bool()) // Transmit packet used data (from TxEthMAC)
@@ -18,19 +17,7 @@ val TxDoneIn = Input(Bool()) // Transmit packet do
val TxAbortIn = Input(Bool()) // Transmit packet abort (input from TxEthMAC)
val PadIn = Input(Bool()) // Padding (input from registers)
val CrcEnIn = Input(Bool()) // Crc append (input from registers)
val RxData = Input(UInt(8.W)) // Receive Packet Data (from RxEthMAC)
val RxValid = Input(Bool()) // Received a valid packet
val RxStartFrm = Input(Bool()) // Receive packet start frame (input from RxEthMAC)
val RxEndFrm = Input(Bool()) // Receive packet end frame (input from RxEthMAC)
val ReceiveEnd = Input(Bool()) // End of receiving of the current packet (input from RxEthMAC)
val ReceivedPacketGood = Input(Bool()) // Received packet is good
val ReceivedLengthOK = Input(Bool()) // Length of the received packet is OK
val TxFlow = Input(Bool()) // Tx flow control (from registers)
val RxFlow = Input(Bool()) // Rx flow control (from registers)
val DlyCrcEn = Input(Bool()) // Delayed CRC enabled (from registers)
val TxPauseTV = Input(UInt(16.W)) // Transmit Pause Timer Value (from registers)
val MAC = Input(UInt(48.W)) // MAC address (from registers)
val RxStatusWriteLatched_sync2 = Input(Bool())
val TxDataOut = Output(UInt(8.W)) // Transmit Packet Data (to TxEthMAC)
val TxStartFrmOut = Output(Bool()) // Transmit packet start frame (output to TxEthMAC)
@@ -40,12 +27,6 @@ val TxAbortOut = Output(Bool()) // Transmit packet ab
val TxUsedDataOut = Output(Bool()) // Transmit packet used data (to host)
val PadOut = Output(Bool()) // Padding (output to TxEthMAC)
val CrcEnOut = Output(Bool()) // Crc append (output to TxEthMAC)
val WillSendControlFrame = Output(Bool())
val TxCtrlEndFrm = Output(Bool())
val ReceivedPauseFrm = Output(Bool())
val ControlFrmAddressOK = Output(Bool())
val SetPauseTimer = Output(Bool())
}
@@ -53,389 +34,17 @@ val SetPauseTimer = Output(Bool())
class MacControl extends RawModule{
val io: MacControlIO = IO(new MacControlIO)
val Pause_wire = Wire(Bool())
val SlotFinished = Wire(Bool())
// Reserved multicast address and Type/Length for PAUSE control
val ReservedMulticast = "h0180C2000001".U(48.W)
val TypeLength = "h8808".U(16.W)
val DecrementPauseTimer = Wire(Bool())
val PauseTimerEq0 = Wire(Bool())
val ControlEnd = Wire(Bool())
val MuxedCtrlData = Wire(UInt(8.W))
val EnableCnt = Wire(Bool())
withClockAndReset( io.MTxClk.asClock, io.asyncReset ) {
val BlockTxDone = RegInit(false.B)
val SendingCtrlFrm = RegInit(false.B) // Sending Control Frame (enables padding and CRC)
val CtrlMux = RegInit(false.B)
val ControlData = RegInit(0.U(8.W))
val TxCtrlStartFrm = RegInit(false.B)
val DlyCrcCnt = RegInit(0.U(4.W))
val ByteCnt = RegInit(0.U(6.W))
val ControlEnd_q = RegNext(ControlEnd)
val TxCtrlStartFrm_q = RegNext(TxCtrlStartFrm)
val TxCtrlEndFrm = RegNext(ControlEnd | ControlEnd_q, false.B); io.TxCtrlEndFrm := TxCtrlEndFrm // Generation of the transmit control packet end frame
val TxUsedDataIn_q = RegNext(io.TxUsedDataIn, false.B)
val WillSendControlFrame = RegInit(false.B); io.WillSendControlFrame := WillSendControlFrame // A command for Sending the control frame is active (latched)
val TxUsedDataOutDetected = RegInit(false.B)
// Synchronization of the pause timer
val PauseTimerEq0_sync1 = RegNext(PauseTimerEq0, true.B)
val PauseTimerEq0_sync2 = RegNext(PauseTimerEq0_sync1, true.B)
val Pause = RegInit(false.B); Pause_wire := Pause // Pause signal generation
when((io.TxDoneIn | io.TxAbortIn | ~TxUsedDataOutDetected) & ~io.TxStartFrmOut){
Pause := io.RxFlow & ~PauseTimerEq0_sync2
}
// Signal TxUsedDataOut was detected (a transfer is already in progress)
when(io.TxDoneIn | io.TxAbortIn){
TxUsedDataOutDetected := false.B
} .elsewhen(io.TxUsedDataOut){
TxUsedDataOutDetected := true.B
}
// Latching variables
val TxAbortInLatched = RegNext(io.TxAbortIn, false.B)
val TxDoneInLatched = RegNext(io.TxDoneIn, false.B)
val MuxedAbort = RegInit(false.B) // Generating muxed abort signal
when(io.TxStartFrmIn){
MuxedAbort := false.B
} .elsewhen(io.TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected){
MuxedAbort := true.B
}
val MuxedDone = RegInit(false.B) // Generating muxed done signal
when(io.TxStartFrmIn){
MuxedDone := false.B
} .elsewhen(io.TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected){
MuxedDone := true.B
}
when(TxCtrlEndFrm & CtrlMux){
WillSendControlFrame := false.B
} .elsewhen(io.TPauseRq & io.TxFlow){
WillSendControlFrame := true.B
}
// Generation of the transmit control packet start frame
when(TxUsedDataIn_q & CtrlMux){
TxCtrlStartFrm := false.B
} .elsewhen(WillSendControlFrame & ~io.TxUsedDataOut & (io.TxDoneIn | io.TxAbortIn | io.TxStartFrmIn | (~TxUsedDataOutDetected))){
TxCtrlStartFrm := true.B
}
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
when(WillSendControlFrame & ~io.TxUsedDataOut){
CtrlMux := true.B
} .elsewhen(io.TxDoneIn){
CtrlMux := false.B
}
// Generation of the Sending Control Frame signal (enables padding and CRC)
when(WillSendControlFrame & TxCtrlStartFrm){
SendingCtrlFrm := true.B
} .elsewhen(io.TxDoneIn){
SendingCtrlFrm := false.B
}
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
when(TxCtrlStartFrm){
BlockTxDone := true.B
} .elsewhen(io.TxStartFrmIn){
BlockTxDone := false.B
}
val IncrementDlyCrcCnt = CtrlMux & io.TxUsedDataIn & ~DlyCrcCnt.extract(2)
val ResetByteCnt = io.asyncReset.asBool | (~TxCtrlStartFrm & (io.TxDoneIn | io.TxAbortIn))
// Delayed CRC counter
when(ResetByteCnt){
DlyCrcCnt := 0.U
} .elsewhen(IncrementDlyCrcCnt){
DlyCrcCnt := DlyCrcCnt + 1.U
}
val IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~io.TxUsedDataIn | io.TxUsedDataIn & ~ControlEnd)
val IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & io.TxUsedDataIn // When TxUsedDataIn and CtrlMux are set at the same time
EnableCnt := (~io.DlyCrcEn | io.DlyCrcEn & (DlyCrcCnt(1,0).andR))
// Byte counter
when(ResetByteCnt){
ByteCnt := 0.U
} .elsewhen(IncrementByteCntBy2 & EnableCnt){
ByteCnt := ByteCnt + 2.U
} .elsewhen(IncrementByteCnt & EnableCnt){
ByteCnt := ByteCnt + 1.U
}
ControlEnd := ByteCnt === "h22".U
MuxedCtrlData := // Control data generation (goes to the TxEthMAC module)
Mux1H(Seq(
(ByteCnt === 0.U) -> Mux(~io.DlyCrcEn | io.DlyCrcEn & (DlyCrcCnt(1,0).andR), 1.U, 0.U),
(ByteCnt === 2.U) -> "h80".U,
(ByteCnt === 4.U) -> "hC2".U,
(ByteCnt === 6.U) -> "h00".U,
(ByteCnt === 8.U) -> "h00".U,
(ByteCnt === 10.U) -> "h01".U,
(ByteCnt === 12.U) -> io.MAC(47,40),
(ByteCnt === 14.U) -> io.MAC(39,32),
(ByteCnt === 16.U) -> io.MAC(31,24),
(ByteCnt === 18.U) -> io.MAC(23,16),
(ByteCnt === 20.U) -> io.MAC(15, 8),
(ByteCnt === 22.U) -> io.MAC( 7, 0),
(ByteCnt === 24.U) -> "h88".U, // Type/Length
(ByteCnt === 26.U) -> "h08".U,
(ByteCnt === 28.U) -> "h00".U, // Opcode
(ByteCnt === 30.U) -> "h01".U,
(ByteCnt === 32.U) -> io.TxPauseTV(15,8), // Pause timer value
(ByteCnt === 34.U) -> io.TxPauseTV( 7,0),
))
// Latched Control data
when(~ByteCnt.extract(0)){
ControlData := MuxedCtrlData
}
io.TxDoneOut := Mux(CtrlMux, ((~io.TxStartFrmIn) & (~BlockTxDone) & MuxedDone), ((~io.TxStartFrmIn) & (~BlockTxDone) & io.TxDoneIn)) // TxDoneOut
io.TxAbortOut := Mux(CtrlMux, ((~io.TxStartFrmIn) & (~BlockTxDone) & MuxedAbort), ((~io.TxStartFrmIn) & (~BlockTxDone) & io.TxAbortIn)) // TxAbortOut
io.TxUsedDataOut := ~CtrlMux & io.TxUsedDataIn // TxUsedDataOut
io.TxStartFrmOut := Mux(CtrlMux, TxCtrlStartFrm, (io.TxStartFrmIn & ~Pause)) // TxStartFrmOut
io.TxEndFrmOut := Mux(CtrlMux, TxCtrlEndFrm, io.TxEndFrmIn) // TxEndFrmOut
io.TxDataOut := Mux(CtrlMux, ControlData, io.TxDataIn ) // TxDataOut[7:0]
io.PadOut := io.PadIn | SendingCtrlFrm // PadOut
io.CrcEnOut := io.CrcEnIn | SendingCtrlFrm // CrcEnOut
}
withClockAndReset( io.MRxClk.asClock, io.asyncReset.asAsyncReset ) {
val AddressOK = RegInit(false.B); io.ControlFrmAddressOK := AddressOK // Multicast or unicast address detected
val TypeLengthOK = RegInit(false.B) // Type/Length field contains 0x8808
val DetectionWindow = RegInit(true.B) // Detection of the PAUSE frame is possible within this window
val OpCodeOK = RegInit(false.B) // PAUSE opcode detected (0x0001)
val DlyCrcCnt = RegInit(0.U(3.W))
val ByteCnt = RegInit(0.U(5.W))
val AssembledTimerValue = RegInit(0.U(16.W))
val LatchedTimerValue = RegInit(0.U(16.W))
val ReceivedPauseFrmWAddr = RegInit(false.B)
val PauseTimer = RegInit(0.U(16.W))
val ByteCntEq0 = io.RxValid & ByteCnt === "h0".U
val ByteCntEq1 = io.RxValid & ByteCnt === "h1".U
val ByteCntEq2 = io.RxValid & ByteCnt === "h2".U
val ByteCntEq3 = io.RxValid & ByteCnt === "h3".U
val ByteCntEq4 = io.RxValid & ByteCnt === "h4".U
val ByteCntEq5 = io.RxValid & ByteCnt === "h5".U
val ByteCntEq12 = io.RxValid & ByteCnt === "h0C".U
val ByteCntEq13 = io.RxValid & ByteCnt === "h0D".U
val ByteCntEq14 = io.RxValid & ByteCnt === "h0E".U
val ByteCntEq15 = io.RxValid & ByteCnt === "h0F".U
val ByteCntEq16 = io.RxValid & ByteCnt === "h10".U
val ByteCntEq17 = io.RxValid & ByteCnt === "h11".U
val ByteCntEq18 = io.RxValid & ByteCnt === "h12".U & DetectionWindow
// Address Detection (Multicast or unicast)
when(DetectionWindow & ByteCntEq0){
AddressOK := io.RxData === ReservedMulticast(47,40) | io.RxData === io.MAC(47,40)
} .elsewhen(DetectionWindow & ByteCntEq1){
AddressOK := (io.RxData === ReservedMulticast(39,32) | io.RxData === io.MAC(39,32)) & AddressOK;
} .elsewhen(DetectionWindow & ByteCntEq2){
AddressOK := (io.RxData === ReservedMulticast(31,24) | io.RxData === io.MAC(31,24)) & AddressOK;
} .elsewhen(DetectionWindow & ByteCntEq3){
AddressOK := (io.RxData === ReservedMulticast(23,16) | io.RxData === io.MAC(23,16)) & AddressOK;
} .elsewhen(DetectionWindow & ByteCntEq4){
AddressOK := (io.RxData === ReservedMulticast(15,8) | io.RxData === io.MAC(15,8)) & AddressOK;
} .elsewhen(DetectionWindow & ByteCntEq5){
AddressOK := (io.RxData === ReservedMulticast(7,0) | io.RxData === io.MAC(7,0)) & AddressOK;
} .elsewhen(io.ReceiveEnd){
AddressOK := false.B
}
// TypeLengthOK (Type/Length Control frame detected)
when(DetectionWindow & ByteCntEq12){
TypeLengthOK := ByteCntEq12 & (io.RxData === TypeLength(15,8));
} .elsewhen(DetectionWindow & ByteCntEq13){
TypeLengthOK := ByteCntEq13 & (io.RxData === TypeLength(7,0)) & TypeLengthOK;
} .elsewhen(io.ReceiveEnd){
TypeLengthOK := false.B
}
// Latch Control Frame Opcode
when(ByteCntEq16){
OpCodeOK := false.B
} .otherwise{
when(DetectionWindow & ByteCntEq14){
OpCodeOK := ByteCntEq14 & io.RxData === 0.U
}
when(DetectionWindow & ByteCntEq15){
OpCodeOK := ByteCntEq15 & io.RxData === 1.U & OpCodeOK;
}
}
// ReceivedPauseFrmWAddr (+Address Check)
when(io.ReceiveEnd){
ReceivedPauseFrmWAddr := false.B
} .elsewhen(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK){
ReceivedPauseFrmWAddr := true.B
}
// Assembling 16-bit timer value from two 8-bit data
when(io.RxStartFrm){
AssembledTimerValue := 0.U
} .otherwise{
when(DetectionWindow & ByteCntEq16){
AssembledTimerValue := Cat(io.RxData, AssembledTimerValue(7,0))
}
when(DetectionWindow & ByteCntEq17){
AssembledTimerValue := Cat(AssembledTimerValue(15,8), io.RxData )
}
}
// Detection window (while PAUSE detection is possible)
when(ByteCntEq18){
DetectionWindow := false.B
} .elsewhen(io.ReceiveEnd){
DetectionWindow := true.B
}
// Latching Timer Value
when(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18){
LatchedTimerValue := AssembledTimerValue
} .elsewhen(io.ReceiveEnd){
LatchedTimerValue := 0.U
}
// Delayed CEC counter
when(io.RxValid & io.RxEndFrm){
DlyCrcCnt := 0.U
}.elsewhen(io.RxValid & ~io.RxEndFrm & ~DlyCrcCnt.extract(2)){
DlyCrcCnt := DlyCrcCnt + 1.U
}
val IncrementByteCnt =
io.RxValid & DetectionWindow & ~ByteCntEq18 &
(~io.DlyCrcEn | io.DlyCrcEn & DlyCrcCnt.extract(2))
// Byte counter
when(io.RxEndFrm){
ByteCnt := 0.U
} .elsewhen(IncrementByteCnt){
ByteCnt := ByteCnt + 1.U
}
when(io.SetPauseTimer){
PauseTimer := LatchedTimerValue
} .elsewhen(DecrementPauseTimer){
PauseTimer := PauseTimer - 1.U
}
val Divider2 = RegInit(false.B) // Divider2 is used for incrementing the Slot timer every other clock
when(PauseTimer.orR & io.RxFlow){
Divider2 := ~Divider2
} .otherwise{
Divider2 := false.B
}
val SlotTimer = RegInit(0.U(6.W)) // SlotTimer
when(io.asyncReset.asBool()){
SlotTimer := 0.U
} .elsewhen(Pause_wire & io.RxFlow & Divider2){
SlotTimer := SlotTimer + 1.U
}
val ReceivedPauseFrm = RegInit(false.B); io.ReceivedPauseFrm := ReceivedPauseFrm // Pause Frame received
when(io.RxStatusWriteLatched_sync2 ){
ReceivedPauseFrm := false.B
} .elsewhen(ByteCntEq16 & TypeLengthOK & OpCodeOK){
ReceivedPauseFrm := true.B
}
io.SetPauseTimer :=
io.ReceiveEnd & ReceivedPauseFrmWAddr & io.ReceivedPacketGood & io.ReceivedLengthOK & io.RxFlow
DecrementPauseTimer := SlotFinished & PauseTimer.orR
PauseTimerEq0 := ~PauseTimer.orR
SlotFinished := SlotTimer.andR & Pause_wire & io.RxFlow & Divider2 // Slot is 512 bits (64 bytes)
}
io.TxDoneOut := ((~io.TxStartFrmIn) & io.TxDoneIn) // TxDoneOut
io.TxAbortOut := ((~io.TxStartFrmIn) & io.TxAbortIn) // TxAbortOut
io.TxUsedDataOut := io.TxUsedDataIn // TxUsedDataOut
io.TxStartFrmOut := io.TxStartFrmIn // TxStartFrmOut
io.TxEndFrmOut := io.TxEndFrmIn // TxEndFrmOut
io.TxDataOut := io.TxDataIn // TxDataOut[7:0]
io.PadOut := io.PadIn
io.CrcEnOut := io.CrcEnIn

11
src/main/scala/Switch/mac/MacRx.scala
View File

@@ -13,10 +13,8 @@ class MacRxIO extends Bundle{
val DlyCrcEn = Input(Bool())
val MaxFL = Input(UInt(16.W))
val r_IFG = Input(Bool())
val MAC = Input(UInt(48.W)) // Station Address
val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table
val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table
val ControlFrmAddressOK = Input(Bool())
val RxData = Output(UInt(8.W))
val RxValid = Output(Bool())
@@ -30,7 +28,6 @@ class MacRxIO extends Bundle{
val StatePreamble = Output(Bool())
val StateSFD = Output(Bool())
val StateData = Output(UInt(2.W))
val AddressMiss = Output(Bool())
}
@@ -192,9 +189,7 @@ trait MacRxFAddrCheck { this: MacRxBase =>
val RxCheckEn = io.StateData.orR
val AddressMiss = RegInit(false.B) // This ff holds the "Address Miss" information that is written to the RX BD status.
io.AddressMiss := AddressMiss
@@ -202,11 +197,7 @@ trait MacRxFAddrCheck { this: MacRxBase =>
val CrcHash = RegInit(0.U(6.W))
val CrcHashGood = RegNext(StateData0 & ByteCntEq6) // Latching CRC for use in the hash table
when(ByteCntEq0){
AddressMiss := false.B
} .elsewhen(ByteCntEq7 & RxCheckEn){
AddressMiss := (~((io.ControlFrmAddressOK)));
}
val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0)
val ByteHash =

8
src/main/scala/Switch/mac/MacStatus.scala
View File

@@ -37,9 +37,6 @@ class MacStatusIO extends Bundle{
val r_FullD = Input(Bool())
val RstDeferLatched = Input(Bool())
val ReceivedLengthOK = Output(Bool())
val ReceiveEnd = Output(Bool())
val ReceivedPacketGood = Output(Bool())
val LatchedCrcError = Output(Bool())
val RxLateCollision = Output(Bool())
val DribbleNibble = Output(Bool())
@@ -64,16 +61,11 @@ class MacStatus extends RawModule{
}
io.ReceivedPacketGood := ~LatchedCrcError // ReceivedPacketGood
io.ReceivedLengthOK := io.RxByteCnt >= io.r_MinFL & io.RxByteCnt <= io.r_MaxFL // ReceivedLengthOK
// Time to take a sample
val TakeSample =
(io.RxStateData.orR & ~io.MRxDV)
val LoadRxStatus = RegNext(TakeSample, false.B); io.LoadRxStatus := LoadRxStatus // LoadRxStatus
val ReceiveEnd = RegNext(LoadRxStatus, false.B); io.ReceiveEnd := ReceiveEnd // ReceiveEnd

5
src/main/scala/Switch/mac/MacTx.scala
View File

@@ -280,15 +280,14 @@ trait MacTxCRC{ this: MacTxBase =>
}
class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC {
val MTxD = RegInit(0.U(4.W)); io.MTxD := MTxD
val StopExcessiveDeferOccured = RegInit(false.B)
val StatusLatch = RegInit(false.B)
val TxUsedData = RegNext(StartData(0) | StartData(1), false.B); io.TxUsedData := TxUsedData
val TxDone = RegInit(false.B); io.TxDone := TxDone
val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
val TxDone = RegInit(false.B); io.TxDone := ~io.TxStartFrm & TxDone
val TxAbort = RegInit(false.B); io.TxAbort := ~io.TxStartFrm & TxAbort
val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
io.MTxErr := false.B