Merge branch 'feature_shintop' into statistics

src/main/scala/backBoard/shin/Interface.scala

@@ -42,8 +42,6 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
-  val encryptKey   = UInt(128.W)
-  val isEncrypt    = Bool()
 
   val intEnable = UInt(32.W)
   val intStatus = UInt(32.W)
@@ -207,7 +205,6 @@ class InterfaceIO extends Bundle{
 
   val sync = Output(Vec(4, Bool()))
 
-  val initEncryptor = Valid(UInt(128.W))
 
   val isSoftReset = Output(Bool())
   val intMstTrig  = Input(Vec(2, Bool()))
@@ -293,12 +290,8 @@ abstract class InterfaceBase extends Module{
 
 
 
-      ((0 until 16).map{ i =>
-        (addr === ("h50".U(16.W) + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
-      }) ++
 
       Seq(
-        (addr === "h60".U ) -> cReg.isEncrypt,
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
         (addr === "h72".U ) -> cReg.intEnable(23,16),
@@ -589,14 +582,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
-  cReg.encryptKey :=
-    Cat(
-      (0 until 16).map{ i =>
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
-      }.reverse
-    )
-
-  cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
@@ -1206,8 +1191,6 @@ with InterfaceSystem
   sReg.isDevOnRightModify := io.isDevOnRightModify
   sReg.indexOfRightDev    := io.indexOfRightDev
 
-  io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
-  io.initEncryptor.bits  := cReg.encryptKey
 
 
 }