diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index c1ec329..41c20dd 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -473,14 +473,17 @@ trait InterfaceMCUop{ this: InterfaceBase => cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) ) } + val rplTimeStampTx = RegInit(0.U(16.W)) + mReg.rplTimeStampTx := rplTimeStampTx - - mReg.rplTimeStampTx := - Cat( - RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ), - RegEnable( dataw, 0.U, isEnW & addrw === "h24".U ) - ) + when( io.intMstTrig(0) ){ + rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W) + } .elsewhen( isEnW & addrw === "h25".U ){ + rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) ) + } .elsewhen( isEnW & addrw === "h24".U ){ + rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw ) + } when( isEnW & isSlvMode ){ diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 15dd5c0..9d0e582 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -3,13 +3,13 @@ `define ENABLE_REG_RW_TEST `define ENABLE_DET_TEST `define ENABLE_SET_ADDR_TEST -//`define ENABLE_SM1_SEND_TEST -//`define ENABLE_SMx_SEND_TEST +`define ENABLE_SM1_SEND_TEST +`define ENABLE_SMx_SEND_TEST `define ENABLE_EXCHG_DATA_SEQ_TEST - //`define ENABLE_EXCHG_DATA_SEQ0_TEST - //`define ENABLE_EXCHG_DATA_SEQ1_TEST - //`define ENABLE_EXCHG_DATA_SEQ2_TEST - //`define ENABLE_EXCHG_DATA_BC_TEST + `define ENABLE_EXCHG_DATA_SEQ0_TEST + `define ENABLE_EXCHG_DATA_SEQ1_TEST + `define ENABLE_EXCHG_DATA_SEQ2_TEST + `define ENABLE_EXCHG_DATA_BC_TEST `define ENABLE_SYNC_TEST `define ENABLE_SYNC_SIG0_TEST `define ENABLE_SYNC_SIG1_TEST diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index fd26960..a3a320d 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -182,52 +182,6 @@ class GenPkt(object): f.write("txBuf[%d]=8'h%02X;\n"%(3 + _k, self.pkt_buf[_k])) f.close() - - -def genWriteTransLenCode(gen_name, sm_idx): - return '''\n//写入发送长度\n'''\ - + '''$fdisplay(spidata_file, "--写数据交换长度");\n'''\ - + '''`DEF_%s_sm(txBuf);\n'''%(gen_name, )\ - + '''spi_trans( (`MST_TX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(0)) );\n'''%(sm_idx,)\ - + '''spi_trans( (`MST_RX%d_LEN_ADDR), (`SPI_WRITE), (2), (`IF_IDX(0)) );\n'''%(sm_idx,) - -def genWriteTransPktCode(gen_name, sm_idx): - return '''\n$fdisplay(spidata_file, "<<发包:");\n'''\ - + '''`DEF_%s(txBuf);\n'''%(gen_name, )\ - + '''spi_trans( (`MST_TX%d_ADDR), (`SPI_WRITE), (`DEF_%s_len), (`IF_IDX(0)) );\n'''%(sm_idx, gen_name, ) - -def genTrgTransPktCode(gen_name, sm_idx): - return '''\n//请求发送\n'''\ - + '''$fdisplay(spidata_file, "--请求发送");\n'''\ - + '''txBuf[0+3] = `MST_TX_TRIGGER(%d);\n'''%(sm_idx, )\ - + '''spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );\n''' - -def genReadAckPktCode(gen_name, sm_idx): - return '''\n//等待回包\n'''\ - + '''@(posedge isResp) #5 begin end\n'''\ - + '''$fdisplay(spidata_file, ">>回包:");\n'''\ - + '''spi_trans( (`MST_RX%d_ADDR), (`SPI_READ), (`DEF_%s_len), (`IF_IDX(0)) );\n'''%(sm_idx, gen_name,) - -def genEnableInsertTimeCode(pos, enableTime=True, enableDelay=True): - data = pos & 0x3fff - if enableTime: - data = data | 0x8000 - if enableDelay: - data = data | 0x4000 - return '''//写入替换时间戳替换地址\n'''\ - + '''$fdisplay(spidata_file, "--增加时间戳插入");\n'''\ - + '''txBuf[0+3] = 8'h%x;\n'''%(data & 0xff, )\ - + '''txBuf[1+3] = 8'h%x;\n'''%((data >> 8) & 0xff, )\ - + '''spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) );\n''' - -def genDisableInsertTimeCode(): - return '''\n//清除替换时间戳替换地址\n'''\ - + '''$fdisplay(spidata_file, "--清除时间戳插入");\n'''\ - + '''txBuf[0+3] = 8'h00;\n'''\ - + '''txBuf[1+3] = 8'h00;\n'''\ - + '''spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //清除替换时间戳替换地址寄存器\n''' - - if __name__ == '__main__': genPkt = GenPkt() @@ -364,7 +318,6 @@ if __name__ == '__main__': data[14] = 64 data[15] = 0 - #subPkt参数:索引、索引类型、地址、命令、长度、数据 genPkt.addSubPkt(0x02, 0, 0x0300, 0x1, 4, data) #sm0 genPkt.addSubPkt(0x01, 0, 0x0308, 0x1, 4, data) #sm2