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1SRAM加入仿真随机初始化；2CDR物理层重新对齐包头 3复制粘贴变量错误

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This commit is contained in:
RuigeLee
2024-10-17 15:32:16 +08:00
parent d449980b5b
commit 7e99cf4489
3 changed files with 21 additions and 16 deletions
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5
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -192,6 +192,11 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
| end
| end
|
| initial begin
| for( integer i = 0; i < 1024; i = i + 1 ) begin
| mem[i] = $random;
| end
| end
|
| //Gowin_DPB your_instance_name(
| // .douta(datarA), //output [15:0] douta

6
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -91,9 +91,9 @@ trait CDRInAxis{ this: CDRInBase =>
val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
val header = Reg(UInt((8*HeaderByte).W))
val payloadLen = header(31,16)
val operation = header(15,8)
val param = header( 7,0)
val payloadLen = header(63,52)
val operation = header(51,48)
val param = header(47, 0)
val isArbLock: Bool
val checkSFD = ShiftRegister( shiftData, 8 )

26
src/main/scala/backBoard/shin/ShinSlv.scala
View File

@@ -189,16 +189,16 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
val isDownStreamError: Bool
val downSendSteteNext = Wire( UInt(3.W) )
val downSendStateCurr = RegNext( downSendSteteNext, 0.U )
val downSendStateNext = Wire( UInt(3.W) )
val downSendStateCurr = RegNext( downSendStateNext, 0.U )
downSendSteteNext := Mux1H(Seq(
downSendStateNext := Mux1H(Seq(
( downSendStateCurr === DownSendStateIdle ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ),
( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ),
( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
))
when( downSendStateCurr =/= downSendSteteNext ){
when( downSendStateCurr =/= downSendStateNext ){
downSendCnt := 0.U
} .elsewhen( downStreamCdrOut.io.axis.fire ){
downSendCnt := downSendCnt + 1.U
@@ -242,21 +242,21 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val upNewHead = Reg( new Header_Info_Bundle )
val upRecvSteteNext = Wire( UInt(3.W) )
val upRecvStateCurr = RegNext( upRecvSteteNext, 0.U )
val upRecvStateNext = Wire( UInt(3.W) )
val upRecvStateCurr = RegNext( upRecvStateNext, 0.U )
val upRecvCnt = Reg(UInt(10.W))
val isLastDevice: Bool
upRecvSteteNext := Mux1H(Seq(
upRecvStateNext := Mux1H(Seq(
(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ),
(upRecvStateCurr === UpRecvStateOHead) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
(upRecvStateCurr === UpRecvStateFData) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
))
when( upRecvStateCurr =/= upRecvSteteNext){
when( upRecvStateCurr =/= upRecvStateNext){
upRecvCnt := 0.U
} .elsewhen( upStreamCdrIn.io.axis.fire ){
upRecvCnt := upRecvCnt + 1.U
@@ -294,7 +294,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val isUpNewHeadCreated =
RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateFData, false.B) | //补一拍
RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateFData, false.B) | //补一拍
isLastDownStreamEnd
when( isUpNewHeadCreated ){
@@ -327,15 +327,15 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val isUpStreamError = RegInit( false.B )
when( (upRecvStateCurr === UpRecvStateIdle & upRecvSteteNext === UpRecvStateOHead) | isLastDownStreamEnd ){
when( (upRecvStateCurr === UpRecvStateIdle & upRecvStateNext === UpRecvStateOHead) | isLastDownStreamEnd ){
isUpStreamError := false.B
} .elsewhen( upStreamFifo.io.enq.fire & upStreamFifo.io.enq.bits.tuser ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateIdle ){
} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateIdle ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvSteteNext === UpRecvStateIdle ){
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast & upRecvCnt < 3.U)) ){
@@ -361,7 +361,7 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
val upSendStateNext = Wire( UInt(3.W) )
val upSendStateCurr = RegNext( downSendSteteNext, 0.U )
val upSendStateCurr = RegNext( upSendStateNext, 0.U )
val upSendCnt = Reg(UInt(10.W))