允许正负3个cycle偏移

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -74,50 +74,72 @@ trait CDRInMultiSample{ this: CDRInBase =>
   val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
 
-
   val sampleReg = Wire(Vec(clkNum, Bool()))
+  dontTouch(sampleReg)
   
   for( i <- 0 until clkNum ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
 
-  val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
+  val sampleReg_sync = for( i <- 0 until clkNum ) yield {
+    ShiftRegisters(sampleReg(i), 8)
+  }
+  for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}
   
+  val sampleReg_Align = Wire(Vec(8*clkNum,Bool()))
+  dontTouch(sampleReg_Align)
 
 
   for( i <- 0 until clkNum ){
-    sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
+    sampleReg_Align(i) := sampleReg_sync(i)(7)
   }
 
   for( i <- clkNum until 2*clkNum ){
-    sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
+    sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6)
   }
 
-  /*
+  for( i <- 2*clkNum until 3*clkNum ){
-  val flitReg =
+    sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5)
-    for( i <- 1 until 22 ) yield {
-      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
-      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
-      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
   }
 
-  val asyncSerDat = PopCount(flitReg) >= 11.U
+  for( i <- 3*clkNum until 4*clkNum ){
-  */
+    sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4)
+  }
+
+  for( i <- 4*clkNum until 5*clkNum ){
+    sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3)
+  }
+
+  for( i <- 5*clkNum until 6*clkNum ){
+    sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2)
+  }
+
+  for( i <- 6*clkNum until 7*clkNum ){
+    sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1)
+  }
+
+  for( i <- 7*clkNum until 8*clkNum ){
+    sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0)
+  }
+
+
+
 
   val flitReg =
-    for( i <- 1 until (2*clkNum)-1 ) yield {
+    for( i <- 1 until (8*clkNum)-1 ) yield {
-      (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+      (sampleReg_Align(i-1) & sampleReg_Align(i+0)) |
-      (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+      (sampleReg_Align(i-1) & sampleReg_Align(i+1)) |
-      (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+      (sampleReg_Align(i+0) & sampleReg_Align(i+1))
     }
+  for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
 
   val clearCnt = Reg(UInt(4.W))
   val checkCnt = Reg(UInt(4.W))
-  val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
+  val arbLock = Reg(UInt( (log2Ceil(8*clkNum)).W ))
-  val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
+  val arbCali = Reg(UInt( (log2Ceil(8*clkNum)).W ))
   val isLock = RegInit(false.B)
 
-  when( sampleReg_sync.reduce(_|_) === false.B ){
+  when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
     when( clearCnt =/= 10.U ){
       clearCnt := clearCnt + 1.U
     }
@@ -132,24 +154,55 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
   //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
+  val checkWindow = Wire( Vec(6, Bool()) )
+  dontTouch(checkWindow)
+
+  checkWindow(0) := 
+    Mux1H( (0 until 116).map{ i =>
+      (arbCali === (i+2).U) -> flitReg(i)
+    })
+
+  checkWindow(1) := 
+    Mux1H( (1 until 117).map{ i =>
+      (arbCali === (i+1).U) -> flitReg(i)
+    })
+
+  checkWindow(2) := 
+    Mux1H( (2 until 118).map{ i =>
+      (arbCali === i.U) -> flitReg(i)
+    })
+
+  checkWindow(3) := 
+    Mux1H( (3 until 119).map{ i =>
+      (arbCali === (i-1).U) -> flitReg(i)
+    })
+
+  checkWindow(4) := 
+    Mux1H( (4 until 120).map{ i =>
+      (arbCali === (i-2).U) -> flitReg(i)
+    })
+
+  checkWindow(5) := 
+    Mux1H( (5 until 121).map{ i =>
+      (arbCali === (i-3).U) -> flitReg(i)
+    })
 
-      // val diff = Wire(UInt( (log2Ceil(clkNum)).W ))
-      // diff := arbLock - j.U
   when( ~isLock ){
-        for( i <- 3 until 19 ){
+    for( i <- 50 until 50+16 ){
-          val j = 19 - i - 1
+      val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         arbLock := j.U
         arbCali := j.U
       }
     }
   }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
-        for( i <- 0 until 22 ){
+    assert( arbCali >= 2.U  && arbCali < 118.U )
-          val j = 22 - i -1
+    for( i <- 0 until 5 ){
-          when( flitReg(j) ^ flitReg(j+1) ){
+      val j = 5 - i -1
-            when( (j.U < arbCali) && ((j+3).U >= arbLock) ){
+      when( checkWindow(j) ^ checkWindow(j+1) ){
+        when( j.U < arbCali ){
           arbCali := arbCali - 1.U
-            } .elsewhen( (j.U > arbCali) && (j.U <= arbLock + 3.U) ){
+        } .elsewhen( j.U > arbCali ){
           arbCali := arbCali + 1.U
         }
       }
@@ -157,8 +210,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
   when( ~isLock ){
-    for( i <- 3 until 19 ){
+    for( i <- 50 until 50+16 ){
-      val j = 19 - i - 1
+      val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         isLock := true.B
       }
@@ -170,7 +223,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   val asyncSerDat = 
     Mux1H(
-      (for { i <- 0 until 22 } yield {
+      (for { i <- 2 until 118 } yield {
         (arbCali === i.U) -> flitReg(i+(8))
       })
     )