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This file is auto-generated. - -// This file enables sbt-bloop to create bloop config files. - -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6") - diff --git a/src/main/scala/Switch/DMA.scala b/src/main/scala/Switch/DMA.scala index d6e3d39..0a8dee5 100644 --- a/src/main/scala/Switch/DMA.scala +++ b/src/main/scala/Switch/DMA.scala @@ -17,8 +17,8 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{ val dmaMst = new MacTileLinkMasterIO - val triTx = Input(Bool()) - val triRx = Output(Bool()) + val triTx = Input ( Vec( chn, Bool()) ) + val triRx = Output( Vec( chn, Bool()) ) val r_TxPtr = Input(UInt(32.W)) val r_RxPtr = Input(UInt(32.W)) val r_TxLen = Input(UInt(16.W)) @@ -33,7 +33,7 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend val rxBuff = Module(new RxBuff(8)) val txBuff = Module(new TxBuff(0)) - rxBuff.headerIO.ready := true.B + def stateIdle = 0.U @@ -53,7 +53,7 @@ trait DMAMstFSM{ this: DMAMstBase => stateNxt := Mux1H(Seq( - ( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.valid, stateRx, stateIdle ) ), + ( stateCur === stateIdle ) -> Mux( (io.triTx.foldLeft(false.B)(_|_) & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.valid, stateRx, stateIdle ) ), ( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ), ( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ), )) @@ -93,8 +93,6 @@ trait DMAMstTileLink{ this: DMAMstBase => rxBuff.io.deq.ready := io.dmaMst.A.fire & (stateCur === stateRx) assert( ~(rxBuff.io.deq.ready & ~rxBuff.io.deq.valid) ) - // rxBuff.io.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle - when( io.dmaMst.A.fire ){ dmaAValid := false.B }.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){ @@ -141,14 +139,33 @@ trait DMAMstBuff{ this: DMAMstBase => } } - io.triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast - io.r_RxLen := RegEnable( rxLength, io.triRx ) + val trigRxNum = Reg(UInt((log2Ceil(chn)).W)) + when( rxBuff.mInfo.source.valid ){ + assert( rxBuff.mInfo.source.bits(48) === 1.U ) + trigRxNum := rxBuff.mInfo.source.bits + } + + for( i <- 0 until chn ){ + io.triRx(i) := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U + } + + io.r_RxLen := RegEnable( rxLength, io.triRx.foldLeft(false.B)(_|_) ) txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx txBuff.io.enq.bits.data := io.dmaMst.D.bits.data txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.r_TxPtr, io.dmaMst.A.fire) txBuff.io.enq.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen) + + val trigTxNum = Reg(UInt((log2Ceil(chn)).W)) + val mInfoValid = stateCur === stateTx + + for( i <- 0 until chn ){ + when( io.triTx(i) & io.r_TxLen(i) > 32.U & stateCur === stateIdle ){ + trigTxNum := i.U + } + } + } diff --git a/src/main/scala/Switch/DMARegisters.scala b/src/main/scala/Switch/DMARegisters.scala new file mode 100644 index 0000000..d2ce595 --- /dev/null +++ b/src/main/scala/Switch/DMARegisters.scala @@ -0,0 +1,120 @@ +package Switch + +import chisel3._ +import chisel3.util._ + +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.interrupts._ + +class DmaRegIO(implicit p: Parameters) extends SwitchBundle{ + + val MacAddr = Output(UInt(48.W)) + + + val r_TxPtr = Output( Vec(chn, UInt(32.W)) ) + val r_RxPtr = Output( Vec(chn, UInt(32.W)) ) + val r_TxLen = Output( Vec(chn, UInt(16.W)) ) + val r_RxLen = Input ( Vec(chn, UInt(16.W)) ) + val triTx = Output( Vec( chn, Bool()) ) + val triRx = Input ( Vec( chn, Bool()) ) +} + +class DmaReg(implicit p: Parameters) extends LazyModule with HasSwitchParameters{ + + + + + + // DTS + val dtsdevice = new SimpleDevice("dma",Seq("dma_0")) + + + val configNode = TLRegisterNode( + address = Seq(AddressSet(0x30001000L, 0x00000fffL)), + device = dtsdevice, + concurrency = 1, + beatBytes = 32/8, + executable = true + ) + lazy val module = new DmaRegImp(this) +} + +class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ + + val io: DmaRegIO = IO(new DmaRegIO) + + + + + + + val txPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) } + val rxPtr = for( i <- 0 until chn ) yield { RegInit( "h80002000".U(32.W)) } + val txLen = for( i <- 0 until chn ) yield { RegInit( 65535.U(16.W)) } + // val rxLen = RegInit( 65535.U(16.W)) + val triRx = for( i <- 0 until chn ) yield { RegInit(false.B) } + + for( i <- 0 until chn ) { + io.r_TxPtr(i) := txPtr(i) + io.r_RxPtr(i) := rxPtr(i) + io.r_TxLen(i) := txLen(i) + } + + for( i <- 0 until chn ) { when( io.triRx(i) ) { triRx(i) := true.B } } + + + outer.configNode.regmap( + + + ( 0 << 2 ) -> + RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( + RegField(32) + )), + + ( 1 << 2 ) -> + RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( + RegField(32) + )), + + + // (0 until chn).map{ i => + // ( (10*i + 10) << 2 ) -> + // RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq( + // RegField.w(1, RegWriteFn((valid, data) => { io.triTx(i) := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))), + // RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))) + // )) + // } + + // (0 until chn).map{ i => + // ( (10*i + 11) << 2 ) -> + // RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq( + // RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))), + // RegField.r(16, io.r_RxLen(i), RegFieldDesc("rxLen", "length of rx")), + // )) + // } + + // (0 until chn).map{ i => + // ( (10*i + 12) << 2 ) -> + // RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq( + // RegField(32, txPtr(i), RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))), + // )) + // } + + // (0 until chn).map{ i => + // ( (10*i + 13) << 2 ) -> + // RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq( + // RegField(32, rxPtr(i), RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))), + // )) + // } + + ) + + + + +} + + diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala index a108086..1bcf821 100644 --- a/src/main/scala/Switch/MacRegisters.scala +++ b/src/main/scala/Switch/MacRegisters.scala @@ -1,4 +1,4 @@ -package MAC +package Switch import chisel3._ import chisel3.util._ @@ -52,29 +52,26 @@ class Mac_Config_Bundle extends Bundle{ } - - class MacRegIO extends Mac_Config_Bundle{ val asyncReset = Input(AsyncReset()) - - val r_TxPtr = Output(UInt(32.W)) - val r_RxPtr = Output(UInt(32.W)) - val r_TxLen = Output(UInt(16.W)) - val r_RxLen = Input(UInt(16.W)) - val triTx = Output(Bool()) - val triRx = Input(Bool()) } -class MacReg(implicit p: Parameters) extends LazyModule{ + + +class MacReg(chn: Int)(implicit p: Parameters) extends LazyModule{ + + + + // DTS - val dtsdevice = new SimpleDevice("mac",Seq("mac_0")) + val dtsdevice = new SimpleDevice(s"mac($chn)",Seq(s"mac_($chn)")) val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int)) val configNode = TLRegisterNode( - address = Seq(AddressSet(0x30000000L, 0x000003ffL)), + address = Seq(AddressSet(0x30000000L + 0x100*chn, 0x000000ffL)), device = dtsdevice, concurrency = 1, beatBytes = 32/8, @@ -83,7 +80,7 @@ class MacReg(implicit p: Parameters) extends LazyModule{ lazy val module = new MacRegImp(this) } -class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(outer){ +class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{ val io: MacRegIO = IO(new MacRegIO) val (int, _) = outer.int_node.out(0) @@ -141,17 +138,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out - val txPtr = RegInit( "h80002000".U(32.W)) - val rxPtr = RegInit( "h80002000".U(32.W)) - val txLen = RegInit( 65535.U(16.W)) - // val rxLen = RegInit( 65535.U(16.W)) - val triRx = RegInit(false.B) - - io.r_TxPtr := txPtr - io.r_RxPtr := rxPtr - io.r_TxLen := txLen - when( io.triRx ) { triRx := true.B } - outer.configNode.regmap( @@ -207,28 +193,13 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out RegField(7, IPGR2, RegFieldDesc("IPGR2", "IPGR2", reset=Some(0x12))) )), - ( 6 << 2 ) -> - RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq( - RegField.r(16, 0.U, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))), - RegField.r(16, 64.U, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))), - )), ( 7 << 2 ) -> RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq( RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))), RegField.r(10,0.U), RegField.r(4, 0.U, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))), )), - ( 8 << 2 ) -> - RegFieldGroup("TX_BD_NUM", Some("Transmit BD Number Register"), Seq( - RegField.r(8, 0.U, RegFieldDesc("TX_BD_NUM", "TX_BD_NUM Un-used", reset=Some(0x40))), - )), - ( 9 << 2 ) -> - RegFieldGroup("CTRLMODER", Some("Control Module Mode Register"), Seq( - RegField.r(1, 1.U, RegFieldDesc("PassAll", "Pass All Receive Frames", reset=Some(0))), - RegField.r(1, 0.U , RegFieldDesc("RxFlow", "Receive Flow Control", reset=Some(0))), - RegField.r(1, 0.U , RegFieldDesc("TxFlow", "Transmit Flow Control", reset=Some(0))), - )), ( 10 << 2 ) -> RegFieldGroup("MIIMODER", Some("MII Mode Register"), Seq( @@ -287,33 +258,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out RegField.bytes(HASH1) ), - ( 20 << 2 ) -> - RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq( - RegField.r(8, 0.U, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))), - RegField.r(1, 0.U, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))), - )), - - ( 30 << 2 ) -> - RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq( - RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", "bd", reset=Some(0x0))), - RegField(1, triRx, RegFieldDesc("bd", "bd", reset=Some(0x0))), - )), - - ( 31 << 2 ) -> - RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq( - RegField(16, txLen, RegFieldDesc("txLen", "length of tx", reset=Some(65535))), - RegField.r(16, io.r_RxLen, RegFieldDesc("rxLen", "length of rx")), - )), - - ( 32 << 2 ) -> - RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq( - RegField(32, txPtr, RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))), - )), - - ( 33 << 2 ) -> - RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq( - RegField(32, rxPtr, RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))), - )), ) diff --git a/src/main/scala/Switch/Parameters.scala b/src/main/scala/Switch/Parameters.scala index 514d401..c046b63 100644 --- a/src/main/scala/Switch/Parameters.scala +++ b/src/main/scala/Switch/Parameters.scala @@ -15,9 +15,10 @@ case object SwitchParamsKey extends Field[SwitchSetting] case class SwitchSetting( // isTileLink: Boolean = true - chn: Int = 1 + chn: Int = 3 ){ - + require( chn > 0 , "Error, at least one mac chn!\n" ) + require( chn <= 16, "Error, register address between only 0x000~0x1000, 0x100 for each!\n" ) } trait HasSwitchParameters { diff --git a/src/main/scala/Switch/PiPoBuff.scala b/src/main/scala/Switch/PiPoBuff.scala index 91d77fa..c99f303 100644 --- a/src/main/scala/Switch/PiPoBuff.scala +++ b/src/main/scala/Switch/PiPoBuff.scala @@ -99,49 +99,75 @@ class PiPoBuffBase[T<:Data]( dp: Int, val threshold: Int = 32) extends Module{ +class TxBuff(threshold: Int = 8) extends PiPoBuffBase(2048, threshold) + + + + +class Rx_MuxInfo_Bundle extends Bundle{ + val dest = Valid(UInt((48+1).W)) + val source = Valid(UInt((48+1).W)) + + def isBroadcast = dest.bits.extract(40) +} class RxBuff(threshold: Int = 8) extends PiPoBuffBase(2048, threshold){ - val headerIO = IO(Decoupled(Vec( 20, UInt(8.W) ) )) + val mInfo = IO(new Rx_MuxInfo_Bundle) + val destReg = for( i <- 0 until 2 ) yield { Reg(Vec(6, UInt(8.W))) } + val destValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - - val header = for( i <- 0 until 2 ) yield { Reg(Vec( 20, UInt(8.W) )) } - val hValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } - + val sourceReg = for( i <- 0 until 2 ) yield { Reg(Vec(6, UInt(8.W))) } + val sourceValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } when( io.enq.fire ){ - when( cnt < 20.U ){ - when( isEnqPi ){ header(0)(cnt) := io.enq.bits.data } - .elsewhen( isEnqPo ){ header(1)(cnt) := io.enq.bits.data - } .otherwise{ - assert(false.B, "Assert Failed, Rx Under Run") - } - } + when( cnt < 6.U ){ + when( isEnqPi ){ destReg(0)(cnt) := io.enq.bits.data } + when( isEnqPo ){ destReg(1)(cnt) := io.enq.bits.data } + } .elsewhen( cnt < 12.U ){ + when( isEnqPi ){ sourceReg(0)(cnt-6.U) := io.enq.bits.data } + when( isEnqPo ){ sourceReg(1)(cnt-6.U) := io.enq.bits.data } + } } - when( headerIO.fire ){ - when( isDeqPi ) { hValid(0) := false.B } - when( isDeqPo ) { hValid(1) := false.B } - } .elsewhen( io.enq.fire & cnt === 20.U ){ - when( isEnqPi ) { hValid(0) := true.B } - when( isEnqPo ) { hValid(1) := true.B } + when( io.deq.fire & io.deq.bits.isLast ){ + when( isDeqPi ) { destValid(0) := false.B; sourceValid(0) := false.B } + when( isDeqPo ) { destValid(1) := false.B; sourceValid(1) := false.B } + } .elsewhen( io.enq.fire & cnt === 5.U ){ + when( isEnqPi ) { destValid(0) := true.B } + when( isEnqPo ) { destValid(1) := true.B } + } .elsewhen( io.enq.fire & cnt === 11.U ){ + when( isEnqPi ) { sourceValid(0) := true.B } + when( isEnqPo ) { sourceValid(1) := true.B } } + mInfo.dest.valid := + Mux1H(Seq( + isDeqPi -> destValid(0), + isDeqPo -> destValid(1), + )) + + mInfo.dest.bits := + Mux1H(Seq( + isDeqPi -> Cat(destReg(0)), + isDeqPo -> Cat(destReg(1)), + )) + + mInfo.source.valid := + Mux1H(Seq( + isDeqPi -> sourceValid(0), + isDeqPo -> sourceValid(1), + )) + + mInfo.source.bits := + Mux1H(Seq( + isDeqPi -> Cat(sourceReg(0)), + isDeqPo -> Cat(sourceReg(1)), + )) - headerIO.valid := - Mux1H(Seq( - isDeqPi -> hValid(0), - isDeqPo -> hValid(1), - )) - - headerIO.bits := - Mux1H(Seq( - isDeqPi -> header(0), - isDeqPo -> header(1), - )) } -class TxBuff(threshold: Int = 8) extends PiPoBuffBase(2048, threshold) + diff --git a/src/main/scala/Switch/Robin.scala b/src/main/scala/Switch/Robin.scala new file mode 100644 index 0000000..4e73809 --- /dev/null +++ b/src/main/scala/Switch/Robin.scala @@ -0,0 +1,65 @@ + +package Switch + +import chisel3._ +import chisel3.util._ +import chisel3.util.random._ + + +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ + +import MAC._ + +class Robin_Bundle extends Bundle{ + val rx = Decoupled(new Mac_Stream_Bundle) + val mInfo = new Rx_MuxInfo_Bundle +} + +class Robin(implicit p: Parameters) extends SwitchModule{ + class RobinIO extends Bundle{ + val enq = Vec( chn+1, Flipped(new Robin_Bundle) ) + val deq = new Robin_Bundle + } + + val io: RobinIO = IO(new RobinIO) + + + + + val isLock = RegInit(false.B) + + val lfsr = LFSR(chn+1, ~isLock) + + for( i <- 0 until chn+1 ) { + when( i.U === lfsr ){ + when( io.enq(i).mInfo.dest.valid ){ + assert( ~isLock ) + isLock := true.B + } + } + } + + when( io.deq.rx.fire & io.deq.rx.bits.isLast ){ + assert( isLock ) + isLock := false.B + } + + + for( i <- 0 until chn+1 ) { + io.enq(i).rx.ready := false.B + } + when( ~isLock ){ + io.deq.rx.valid := false.B + io.deq.rx.bits := 0.U.asTypeOf(new Mac_Stream_Bundle) + io.deq.mInfo.dest.valid := false.B + io.deq.mInfo.dest.bits := 0.U + io.deq.mInfo.source.valid := false.B + io.deq.mInfo.source.bits := 0.U + } .otherwise{ + io.deq <> io.enq(lfsr) + } + + +} \ No newline at end of file diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala index a54b055..bf597d3 100644 --- a/src/main/scala/Switch/Switch.scala +++ b/src/main/scala/Switch/Switch.scala @@ -33,7 +33,8 @@ class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters - val ethReg = LazyModule(new MacReg) + val macReg = for( i <- 0 until chn ) yield { LazyModule(new MacReg(i)) } + val dmaReg = LazyModule(new DmaReg) lazy val module = new SwitchImp(this) @@ -51,23 +52,22 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out mac(i).io.mii <> io.mii(i) mac(i).io.asyncReset := io.asyncReset io.isLoopBack(i) := mac(i).io.isLoopBack + + outer.macReg(i).module.io.asyncReset := io.asyncReset + outer.macReg(i).module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(i).io.cfg } - outer.ethReg.module.io.asyncReset := io.asyncReset - outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg - - val dmaMst = Module(new DmaNode(dma_edge)) - dmaMst.io.triTx := outer.ethReg.module.io.triTx - outer.ethReg.module.io.triRx := dmaMst.io.triRx + dmaMst.io.triTx := outer.dmaReg.module.io.triTx + outer.dmaReg.module.io.triRx := dmaMst.io.triRx - dmaMst.io.r_TxPtr := outer.ethReg.module.io.r_TxPtr - dmaMst.io.r_RxPtr := outer.ethReg.module.io.r_RxPtr - dmaMst.io.r_TxLen := outer.ethReg.module.io.r_TxLen - outer.ethReg.module.io.r_RxLen := dmaMst.io.r_RxLen + dmaMst.io.r_TxPtr := outer.dmaReg.module.io.r_TxPtr + dmaMst.io.r_RxPtr := outer.dmaReg.module.io.r_RxPtr + dmaMst.io.r_TxLen := outer.dmaReg.module.io.r_TxLen + outer.dmaReg.module.io.r_RxLen := dmaMst.io.r_RxLen dmaMst.io.dmaMst.D.bits := dma_bus.d.bits dmaMst.io.dmaMst.D.valid := dma_bus.d.valid @@ -79,13 +79,91 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out + val robin = Module(new Robin) + + // dmaMst.ex.tx <> + // <> mac(0).ex.tx + + for( i <- 0 until chn ){ + mac(i).ex.rx <> robin.io.enq(i).rx + mac(i).ex.mInfo <> robin.io.enq(i).mInfo + } + + dmaMst.ex.rx <> robin.io.enq(chn+1-1).rx + dmaMst.ex.mInfo <> robin.io.enq(chn+1-1).mInfo - dmaMst.ex.tx <> mac(0).ex.rx - dmaMst.ex.rx <> mac(0).ex.tx + val destTable = Wire( Vec( chn+1, Vec( 4, UInt(48.W) ) ) ) + for( i <- 0 until chn+1 ){ + destTable(i)(0) := "h102030405A00".U + i.U + destTable(i)(1) := "h102030405B00".U + i.U + destTable(i)(2) := "h102030405C00".U + i.U + destTable(i)(3) := "h102030405D00".U + i.U + } + val isHit = Reg(Bool()) + val destChn = Reg(UInt((log2Ceil(chn+1)).W)) + val isMuxBusy = RegInit(false.B) + + + when( robin.io.deq.rx.fire & robin.io.deq.rx.bits.isLast ){ + assert( isMuxBusy ) + isMuxBusy := false.B + } .elsewhen( robin.io.deq.mInfo.dest.valid ){ + assert( ~isMuxBusy ) + isMuxBusy := true.B + + + isHit := false.B + for( i <- 0 until chn+1 ){ + when( + robin.io.deq.mInfo.dest.bits === destTable(i)(0) || + robin.io.deq.mInfo.dest.bits === destTable(i)(1) || + robin.io.deq.mInfo.dest.bits === destTable(i)(2) || + robin.io.deq.mInfo.dest.bits === destTable(i)(3) + ){ + isHit := true.B + destChn := i.U + } + } + + } + + val tempTxPort = Wire( Vec( chn+1, Decoupled(new Mac_Stream_Bundle) ) ) + for( i <- 0 until chn ){ + mac(i).ex.tx.valid := tempTxPort(i).valid + mac(i).ex.tx.bits := tempTxPort(i).bits + tempTxPort(i).ready := mac(i).ex.tx.ready + } + dmaMst.ex.tx.valid := tempTxPort(chn+1-1).valid + dmaMst.ex.tx.bits := tempTxPort(chn+1-1).bits + tempTxPort(chn+1-1).ready := dmaMst.ex.tx.ready + + + val allTxReady = tempTxPort.map{ x => x.ready }.foldLeft(true.B)(_&_) + + + for( i <- 0 until chn+1 ){ + tempTxPort(chn+1-1).valid := false.B + tempTxPort(chn+1-1).bits := 0.U.asTypeOf(new Mac_Stream_Bundle) + } + robin.io.deq.rx.ready := false.B + + when( isMuxBusy ){ + when( isHit ){ + tempTxPort(destChn).valid := robin.io.deq.rx.valid + tempTxPort(destChn).bits := robin.io.deq.rx.bits + robin.io.deq.rx.ready := tempTxPort(destChn).ready + } .otherwise{ + for( i <- 0 until chn+1 ){ + tempTxPort(i).valid := robin.io.deq.rx.valid & allTxReady + tempTxPort(i).bits := robin.io.deq.rx.bits + } + robin.io.deq.rx.ready := allTxReady + } + } } diff --git a/src/main/scala/Switch/SwitchNode.scala b/src/main/scala/Switch/SwitchNode.scala index b105bbd..177e11c 100644 --- a/src/main/scala/Switch/SwitchNode.scala +++ b/src/main/scala/Switch/SwitchNode.scala @@ -10,13 +10,11 @@ import freechips.rocketchip.tilelink._ import MAC._ -class Rx_MuxInfo_Bundle extends Bundle{ -} class SwitchNodeIO extends Bundle{ val rx = Decoupled(new Mac_Stream_Bundle) - val dest = Output(new Rx_MuxInfo_Bundle) + val mInfo = new Rx_MuxInfo_Bundle val tx = Flipped(Decoupled(new Mac_Stream_Bundle)) @@ -35,7 +33,7 @@ class MacNode(implicit p: Parameters) extends Mac{ val rxBuff = Module(new RxBuff) val txBuff = Module(new TxBuff) - rxBuff.headerIO.ready := true.B + macTileLinkRx.io.rxEnq <> rxBuff.io.enq txBuff.io.deq <> macTileLinkTx.io.txDeq @@ -43,13 +41,22 @@ class MacNode(implicit p: Parameters) extends Mac{ rxBuff.io.deq <> ex.rx ex.tx <> txBuff.io.enq - ex.dest := DontCare + + ex.mInfo <> rxBuff.mInfo } class DmaNode(edgeOut: TLEdgeOut)(implicit p: Parameters) extends DMAMst(edgeOut){ + def DmaMac = "habcdef".U(48.W) + ex.tx <> rxBuff.io.enq txBuff.io.deq <> ex.rx + + ex.mInfo.dest.valid := mInfoValid + ex.mInfo.dest.bits := Cat( 1.U, trigTxNum ) + ex.mInfo.source.valid := mInfoValid + ex.mInfo.source.bits := DmaMac + } diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala index c9fc6b0..26cdca8 100644 --- a/src/main/scala/Switch/WithSwitch.scala +++ b/src/main/scala/Switch/WithSwitch.scala @@ -14,9 +14,15 @@ trait WithSwitchMix { this: BaseSubsystem => sbus.coupleFrom("switch_mst") { _ := TLBuffer() := TLWidthWidget(8 / 8) := switch.tlClientNode } // pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ } - pbus.coupleTo("switch_cfg") { switch.ethReg.configNode := TLFragmenter(pbus) := _ } - ibus.fromSync := switch.ethReg.int_node + for( i <- 0 until 3 ){ + pbus.coupleTo("switch_cfg") { switch.macReg(i).configNode := TLFragmenter(pbus) := _ } + ibus.fromSync := switch.macReg(i).int_node + } + + pbus.coupleTo("switch_cfg") { switch.dmaReg.configNode := TLFragmenter(pbus) := _ } + + }