From 7d39514eb80bdd51f94b9ef6faf49151ec7ab7a1 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 8 Aug 2025 16:28:39 +0800
Subject: [PATCH] =?UTF-8?q?=E5=BA=8F=E5=88=97=E5=8F=B7=E5=8C=BA=E5=9F=9F?=
 =?UTF-8?q?=E6=8B=89=E5=88=B0=E9=A1=B6=E5=B1=82?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 21 ++++++++++++-------
 src/main/scala/backBoard/shin/ShinTop.scala   |  4 ++++
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index c1e812a..11ec80f 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -42,6 +42,8 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
+  val uniCode = UInt(64.W)
+
   val softResetCode = Vec(4, UInt(8.W))
 
   val intEnable = UInt(32.W)
@@ -195,6 +197,9 @@ class InterfaceIO extends Bundle{
 
   val latchPin = Input(Vec(2, Bool()))
   val isPoReset = Output(Bool())
+
+  val hwSerial  = Input(UInt(48.W))
+  val uniCode   = Input(UInt(64.W))
 }
 
 
@@ -232,7 +237,11 @@ abstract class InterfaceBase extends Module{
       ((0 until 6).map{ i =>
         (addr === ("h2".U(16.W) + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0 )
       }) ++
-      
+
+      ((0 until 8).map{ i =>
+        (addr === ("h10".U(16.W) + i.U) ) -> cReg.uniCode( 8*i+7,8*i+0 )
+      }) ++
+
       Seq(
         (addr === "h8".U )  -> cReg.busRate( 7,0 ),
         (addr === "h9".U )  -> cReg.spiSel,
@@ -588,14 +597,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
 
   cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U )
-  cReg.hwVersion := RegEnable( dataw     , "hF0".U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U )
 
-  cReg.hwSerial := 
-    Cat(
-      (0 until 6).map{ i =>
-      RegEnable( dataw, "haa".U, isEnW & addrw === ("h2".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
-      }.reverse
-    )
   
   cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
@@ -1388,6 +1390,9 @@ with InterfaceWdt
 with InterfaceSystem
 with InterfaceEvent
 {
+  cReg.hwVersion := "h1".U
+  cReg.hwSerial := io.hwSerial
+  cReg.uniCode := io.uniCode
 
 
   io.txReq.bits.txSM  := mReg.txSM
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index e44a44c..ce1ecb3 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -29,6 +29,8 @@ class ShinTopIO extends Bundle{
   val interrupt = Output(Bool())
 
   val latchPin = Input(Vec(2, Bool()))
+  val hwSerial = Input(UInt(48.W))
+  val uniCode = Input(UInt(64.W))
 }
 
 
@@ -50,6 +52,8 @@ abstract class ShinTopBase extends Module{
   val interface = Module(new Interface)
 
   interface.io.latchPin  := io.latchPin
+  interface.io.uniCode   := io.uniCode
+  interface.io.hwSerial  := io.hwSerial
 
   interface.io.intTransEnd(0) := downCDRIn.io.axis.fire  & downCDRIn.io.axis.bits.tlast
   interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast